Andrew Turner
c84261da6f
Add an initial driver for the GICv5 interrupt controller. This provides host-only support for the GICv5 interrupt controller. It is specified in the ARM-AES-0070 document & based on version 00eac0. In the GICv5 there are 3 interrupt spaces: PPI, SPI, and LPI. Unlike previous interrupt controllers they don't share a single interrupt ID range, so PPI IRQ 1 and SPI IRQ 1 are different interrupts. There is a common irqsrc stricture that encodes this information as it is common across the interrupt types. Unlike previous GIC versions there are no software generated interrupts that can target a configurable collection of CPUs. These have been replaced with LPIs, where each CPU will have one allocated for each IPI type. This driver handles the CPU interface and interrupt routing service (IRS). The CPU interface provides the interface to manage and handle interrupts, while the IRS handles routing LPIs and SPIs to the target CPU. Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D54250
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