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Import device-tree files from Linux 7.1

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Emmanuel Vadot committed 2026-08-27 09:08:15 +02:00
1 parent 070a687a2a
commit e541832e0c
1304 files changed
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Bindings/arm/altera.yaml
+7
View File
@@ -84,6 +84,12 @@ properties:
- altr,socfpga-stratix10-swvp
- const: altr,socfpga-stratix10
- description: Stratix 10 SoCDK eMMC variant
items:
- const: altr,socfpga-stratix10-socdk-emmc
- const: altr,socfpga-stratix10-socdk
- const: altr,socfpga-stratix10
- description: AgileX boards
items:
- enum:
@@ -105,6 +111,7 @@ properties:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-013b
- intel,socfpga-agilex5-socdk-modular
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
Bindings/arm/arm,coresight-cti.yaml
+3
View File
@@ -128,6 +128,9 @@ properties:
"#address-cells":
const: 1
access-controllers:
maxItems: 1
patternProperties:
'^trig-conns@([0-9]+)$':
type: object
Bindings/arm/arm,coresight-dynamic-funnel.yaml
+3
View File
@@ -78,6 +78,9 @@ properties:
description: Output connection to CoreSight Trace bus
$ref: /schemas/graph.yaml#/properties/port
access-controllers:
maxItems: 1
required:
- compatible
- reg
Bindings/arm/arm,coresight-etm.yaml
+3
View File
@@ -118,6 +118,9 @@ properties:
description: Output connection from the ETM to CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
access-controllers:
maxItems: 1
required:
- compatible
- clocks
Bindings/arm/arm,coresight-stm.yaml
+3
View File
@@ -73,6 +73,9 @@ properties:
description: Output connection to the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
access-controllers:
maxItems: 1
required:
- compatible
- reg
Bindings/arm/arm,coresight-tmc.yaml
+3
View File
@@ -128,6 +128,9 @@ properties:
- const: tracedata
- const: metadata
access-controllers:
maxItems: 1
required:
- compatible
- reg
Bindings/arm/arm,coresight-tpiu.yaml
+3
View File
@@ -70,6 +70,9 @@ properties:
description: Input connection from the CoreSight Trace bus.
$ref: /schemas/graph.yaml#/properties/port
access-controllers:
maxItems: 1
required:
- compatible
- reg
Bindings/arm/arm,corstone1000.yaml
+10 -5
View File
@@ -15,11 +15,11 @@ description: |+
provides a flexible compute architecture that combines Cortex‑A and Cortex‑M
processors.
Support for Cortex‑A32, Cortex‑A35 and Cortex‑A53 processors. Two expansion
systems for M-Class (or other) processors for adding sensors, connectivity,
video, audio and machine learning at the edge System and security IPs to build
a secure SoC for a range of rich IoT applications, for example gateways, smart
cameras and embedded systems.
Support for Cortex‑A32, Cortex‑A35, Cortex‑A53 and Cortex-A320 processors.
Two expansion systems for M-Class (or other) processors for adding sensors,
connectivity, video, audio and machine learning at the edge System and
security IPs to build a secure SoC for a range of rich IoT applications, for
example gateways, smart cameras and embedded systems.
Integrated Secure Enclave providing hardware Root of Trust and supporting
seamless integration of the optional CryptoCell™-312 cryptographic
@@ -39,6 +39,11 @@ properties:
implementation of this system. See ARM ecosystems FVP's.
items:
- const: arm,corstone1000-fvp
- description: Corstone1000-A320 FVP is the Fixed Virtual Platform
implementation of this system with Cortex-A320 cores and Ethos-U85
NPU. See ARM ecosystems FVP's.
items:
- const: arm,corstone1000-a320-fvp
additionalProperties: true
Bindings/arm/arm,vexpress-juno.yaml
+10
View File
@@ -119,6 +119,16 @@ properties:
items:
- const: arm,foundation-aarch64
- const: arm,vexpress
- description: Arm Zena Compute Subsystem Platforms
Arm Zena Compute Subsystem (CSS) is a compute platform targeting
the automotive sector. Arm Zena CSS is a high-performance Arm
Cortex-A720AE Application Processor system augmented with an Arm
Cortex-R82AE based Safety Island and real-time domain.
items:
- enum:
- arm,zena-css-fvp
- const: arm,zena-css
- const: arm,vexpress
arm,vexpress,position:
description: When daughterboards are stacked on one site, their position
Bindings/arm/arm,vexpress-scc.yaml
+53
View File
@@ -0,0 +1,53 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/arm,vexpress-scc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Express Serial Configuration Controller
maintainers:
- Liviu Dudau <[email protected]>
- Sudeep Holla <[email protected]>
description: |
Test chips for ARM Versatile Express platform implement SCC (Serial
Configuration Controller) interface, used to set initial conditions
for the test chip.
In some cases its registers are also mapped in normal address space
and can be used to obtain runtime information about the chip internals
(like silicon temperature sensors) and as interface to other subsystems
like platform configuration control and power management.
properties:
compatible:
items:
- enum:
- arm,vexpress-scc,v2p-ca15_a7
- const: arm,vexpress-scc
reg:
maxItems: 1
interrupts:
maxItems: 1
required:
- compatible
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
scc@7fff0000 {
compatible = "arm,vexpress-scc,v2p-ca15_a7", "arm,vexpress-scc";
reg = <0 0x7fff0000 0 0x1000>;
interrupts = <0 95 4>;
};
};
...
Bindings/arm/aspeed/aspeed.yaml
+2
View File
@@ -35,6 +35,7 @@ properties:
- ampere,mtjade-bmc
- aspeed,ast2500-evb
- asrock,altrad8-bmc
- asrock,ast2500-paul-ipmi-card
- asrock,e3c246d4i-bmc
- asrock,e3c256d4i-bmc
- asrock,romed8hm3-bmc
@@ -80,6 +81,7 @@ properties:
- ampere,mtmitchell-bmc
- aspeed,ast2600-evb
- aspeed,ast2600-evb-a1
- asus,ast2600-kommando-ipmi-card
- asus,x4tf-bmc
- facebook,anacapa-bmc
- facebook,bletchley-bmc
Bindings/arm/atmel,at91rm9200-sdramc.yaml
+66
View File
@@ -0,0 +1,66 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-sdramc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip (Atmel) SDRAM / DDR Controller (RAMC / DDRAMC / UDDRC)
maintainers:
- Nicolas Ferre <[email protected]>
- Claudiu Beznea <[email protected]>
description:
The SDRAM/DDR Controller (often called RAMC or DDRAMC) in various
Atmel/Microchip ARM9 and Cortex-A5/A7 SoCs manages external
SDRAM / DDR memory. It is typically exposed as a syscon node for
register access from other drivers (e.g. for initialization or mode
configuration). No interrupts or clocks are usually required in the
binding.
properties:
compatible:
oneOf:
- items:
- const: atmel,at91rm9200-sdramc
- const: syscon
- items:
- const: microchip,sama7d65-uddrc
- const: microchip,sama7g5-uddrc
- enum:
- atmel,at91sam9260-sdramc
- atmel,at91sam9g45-ddramc
- atmel,sama5d3-ddramc
- microchip,sam9x60-ddramc
- microchip,sam9x7-ddramc
- microchip,sama7g5-uddrc
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: ddrck
- const: mpddr
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/at91.h>
ramc@ffffe400 {
compatible = "atmel,at91sam9g45-ddramc";
reg = <0xffffe400 0x200>;
clocks = <&pmc PMC_TYPE_SYSTEM 2>;
clock-names = "ddrck";
};
...
Bindings/arm/atmel,at91rm9200-st.yaml
+69
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@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel,at91rm9200-st.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel System Timer
maintainers:
- Nicolas Ferre <[email protected]>
- Claudiu Beznea <[email protected]>
description:
The System Timer (ST) module in AT91RM9200 provides periodic tick and
alarm capabilities. It is exposed as a simple multi-function device
(simple-mfd + syscon) because it shares its register space and interrupt
with other System Controller blocks.
properties:
compatible:
items:
- const: atmel,at91rm9200-st
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
patternProperties:
"^watchdog@[0-9a-f]+$":
$ref: /schemas/watchdog/atmel,at91rm9200-wdt.yaml#
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
timer@fffffd00 {
compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd";
reg = <0xfffffd00 0x100>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&slow_xtal>;
#address-cells = <1>;
#size-cells = <1>;
watchdog@fffffd40 {
compatible = "atmel,at91rm9200-wdt";
reg = <0xfffffd40 0x40>;
};
};
...
Bindings/arm/atmel,at91sam9260-pit.yaml
+49
View File
@@ -0,0 +1,49 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/atmel,at91sam9260-pit.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel AT91SAM9260 Periodic Interval Timer (PIT)
maintainers:
- Nicolas Ferre <[email protected]>
- Claudiu Beznea <[email protected]>
description:
The Periodic Interval Timer (PIT) is part of the System Controller of
various Microchip 32-bit ARM-based SoCs (formerly Atmel AT91 series).
It is a simple down-counter timer used mainly as the kernel tick source.
The PIT is clocked from the slow clock and shares a single IRQ line with
other System Controller peripherals.
properties:
compatible:
const: atmel,at91sam9260-pit
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
required:
- compatible
- reg
- interrupts
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
timer@fffffd30 {
compatible = "atmel,at91sam9260-pit";
reg = <0xfffffd30 0x10>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk32k>;
};
...
Bindings/arm/atmel-at91.yaml
+6
View File
@@ -243,6 +243,12 @@ properties:
- const: microchip,lan9668
- const: microchip,lan966
- description: Microchip LAN9696 EV23X71A Evaluation Board
items:
- const: microchip,ev23x71a
- const: microchip,lan9696
- const: microchip,lan9691
- description: Kontron KSwitch D10 MMT series
items:
- enum:
Bindings/arm/axis.yaml
+6
View File
@@ -31,6 +31,12 @@ properties:
- axis,artpec8-grizzly
- const: axis,artpec8
- description: Axis ARTPEC-9 SoC board
items:
- enum:
- axis,artpec9-alfred
- const: axis,artpec9
additionalProperties: true
...
Bindings/arm/cpus.yaml
+156 -143
View File
@@ -79,149 +79,162 @@ properties:
All other bits in the reg cells must be set to 0.
compatible:
enum:
- apm,potenza
- apm,strega
- apple,avalanche
- apple,blizzard
- apple,cyclone
- apple,firestorm
- apple,hurricane-zephyr
- apple,icestorm
- apple,mistral
- apple,monsoon
- apple,twister
- apple,typhoon
- arm,arm710t
- arm,arm720t
- arm,arm740t
- arm,arm7ej-s
- arm,arm7tdmi
- arm,arm7tdmi-s
- arm,arm9es
- arm,arm9ej-s
- arm,arm920t
- arm,arm922t
- arm,arm925
- arm,arm926e-s
- arm,arm926ej-s
- arm,arm940t
- arm,arm946e-s
- arm,arm966e-s
- arm,arm968e-s
- arm,arm9tdmi
- arm,arm1020e
- arm,arm1020t
- arm,arm1022e
- arm,arm1026ej-s
- arm,arm1136j-s
- arm,arm1136jf-s
- arm,arm1156t2-s
- arm,arm1156t2f-s
- arm,arm1176jzf
- arm,arm1176jz-s
- arm,arm1176jzf-s
- arm,arm11mpcore
- arm,armv8 # Only for s/w models
- arm,c1-nano
- arm,c1-premium
- arm,c1-pro
- arm,c1-ultra
- arm,cortex-a5
- arm,cortex-a7
- arm,cortex-a8
- arm,cortex-a9
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
- arm,cortex-a32
- arm,cortex-a34
- arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
- arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a320
- arm,cortex-a510
- arm,cortex-a520
- arm,cortex-a520ae
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-a720
- arm,cortex-a720ae
- arm,cortex-a725
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
- arm,cortex-m3
- arm,cortex-m4
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-r52
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,cortex-x4
- arm,cortex-x925
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
- arm,neoverse-n3
- arm,neoverse-v1
- arm,neoverse-v2
- arm,neoverse-v3
- arm,neoverse-v3ae
- arm,rainier
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
- cavium,thunder
- cavium,thunder2
- faraday,fa526
- intel,sa110
- intel,sa1100
- marvell,feroceon
- marvell,mohawk
- marvell,pj4a
- marvell,pj4b
- marvell,sheeva-v5
- marvell,sheeva-v7
- nvidia,tegra132-denver
- nvidia,tegra186-denver
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo
- qcom,kryo240
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
- qcom,kryo360
- qcom,kryo385
- qcom,kryo465
- qcom,kryo468
- qcom,kryo470
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
- qcom,kryo660
- qcom,kryo670
- qcom,kryo685
- qcom,kryo780
- qcom,oryon
- qcom,scorpion
- samsung,mongoose-m2
- samsung,mongoose-m3
- samsung,mongoose-m5
oneOf:
- enum:
- apm,potenza
- apm,strega
- apple,avalanche
- apple,blizzard
- apple,cyclone
- apple,everest
- apple,firestorm
- apple,hurricane-zephyr
- apple,icestorm
- apple,mistral
- apple,monsoon
- apple,sawtooth
- apple,twister
- apple,typhoon
- arm,arm710t
- arm,arm720t
- arm,arm740t
- arm,arm7ej-s
- arm,arm7tdmi
- arm,arm7tdmi-s
- arm,arm9es
- arm,arm9ej-s
- arm,arm920t
- arm,arm922t
- arm,arm925
- arm,arm926e-s
- arm,arm926ej-s
- arm,arm940t
- arm,arm946e-s
- arm,arm966e-s
- arm,arm968e-s
- arm,arm9tdmi
- arm,arm1020e
- arm,arm1020t
- arm,arm1022e
- arm,arm1026ej-s
- arm,arm1136j-s
- arm,arm1136jf-s
- arm,arm1156t2-s
- arm,arm1156t2f-s
- arm,arm1176jzf
- arm,arm1176jz-s
- arm,arm1176jzf-s
- arm,arm11mpcore
- arm,armv8 # Only for s/w models
- arm,c1-nano
- arm,c1-premium
- arm,c1-pro
- arm,c1-ultra
- arm,cortex-a5
- arm,cortex-a7
- arm,cortex-a8
- arm,cortex-a9
- arm,cortex-a12
- arm,cortex-a15
- arm,cortex-a17
- arm,cortex-a32
- arm,cortex-a34
- arm,cortex-a35
- arm,cortex-a53
- arm,cortex-a55
- arm,cortex-a57
- arm,cortex-a65
- arm,cortex-a72
- arm,cortex-a73
- arm,cortex-a75
- arm,cortex-a76
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
- arm,cortex-a78c
- arm,cortex-a320
- arm,cortex-a510
- arm,cortex-a520
- arm,cortex-a520ae
- arm,cortex-a710
- arm,cortex-a715
- arm,cortex-a720
- arm,cortex-a720ae
- arm,cortex-a725
- arm,cortex-m0
- arm,cortex-m0+
- arm,cortex-m1
- arm,cortex-m3
- arm,cortex-m4
- arm,cortex-r4
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-r52
- arm,cortex-x1
- arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,cortex-x4
- arm,cortex-x925
- arm,neoverse-e1
- arm,neoverse-n1
- arm,neoverse-n2
- arm,neoverse-n3
- arm,neoverse-v1
- arm,neoverse-v2
- arm,neoverse-v3
- arm,neoverse-v3ae
- arm,rainier
- brcm,brahma-b15
- brcm,brahma-b53
- brcm,vulcan
- cavium,thunder
- cavium,thunder2
- faraday,fa526
- intel,sa110
- intel,sa1100
- marvell,feroceon
- marvell,mohawk
- marvell,pj4a
- marvell,pj4b
- marvell,sheeva-v5
- marvell,sheeva-v7
- nvidia,tegra132-denver
- nvidia,tegra186-denver
- nvidia,tegra194-carmel
- qcom,krait
- qcom,kryo240
- qcom,kryo250
- qcom,kryo260
- qcom,kryo280
- qcom,kryo360
- qcom,kryo385
- qcom,kryo465
- qcom,kryo468
- qcom,kryo470
- qcom,kryo485
- qcom,kryo560
- qcom,kryo570
- qcom,kryo660
- qcom,kryo670
- qcom,kryo685
- qcom,kryo780
- qcom,oryon-1-1
- qcom,oryon-1-2
- qcom,oryon-1-3
- qcom,oryon-1-4
- qcom,oryon-2-1
- qcom,oryon-2-2
- qcom,oryon-2-3
- qcom,scorpion
- samsung,mongoose-m2
- samsung,mongoose-m3
- samsung,mongoose-m5
- enum:
- qcom,kryo
- qcom,oryon
# Too generic, do not use in new code
deprecated: true
enable-method:
$ref: /schemas/types.yaml#/definitions/string
Bindings/arm/freescale/fsl,imx51-m4if.yaml
+1
View File
@@ -15,6 +15,7 @@ properties:
compatible:
oneOf:
- enum:
- fsl,imx25-aips
- fsl,imx51-m4if
- fsl,imx51-tigerp
- fsl,imx51-aipstz
Bindings/arm/freescale/fsl,imx7ulp-pm.yaml
+5
View File
@@ -28,6 +28,9 @@ properties:
reg:
maxItems: 1
'#clock-cells':
const: 1
clocks:
maxItems: 2
@@ -39,6 +42,7 @@ properties:
required:
- compatible
- reg
- '#clock-cells'
additionalProperties: false
@@ -47,4 +51,5 @@ examples:
smc1@40410000 {
compatible = "fsl,imx7ulp-smc1";
reg = <0x40410000 0x1000>;
#clock-cells = <1>;
};
Bindings/arm/fsl.yaml
+86
View File
@@ -996,6 +996,14 @@ properties:
- const: engicam,icore-mx8mm # i.MX8MM Engicam i.Core MX8M Mini SoM
- const: fsl,imx8mm
- description: Ka-Ro Electronics TX8M-1610 based boards
items:
- enum:
- gocontroll,moduline-iv-306-d
- gocontroll,moduline-mini-111
- const: karo,tx8m-1610
- const: fsl,imx8mm
- description: Kontron BL i.MX8MM (N801X S) Board
items:
- const: kontron,imx8mm-bl
@@ -1041,6 +1049,13 @@ properties:
- const: phytec,imx8mm-phycore-som # phyCORE-i.MX8MM SoM
- const: fsl,imx8mm
- description: SolidRun i.MX8MM SoM based boards
items:
- enum:
- solidrun,imx8mm-hummingboard-ripple # SolidRun i.MX8MM SoM on HummingBoard Ripple
- const: solidrun,imx8mm-sr-som
- const: fsl,imx8mm
- description: Variscite VAR-SOM-MX8MM based boards
items:
- const: variscite,var-som-mx8mm-symphony
@@ -1069,6 +1084,7 @@ properties:
- fsl,imx8mn-ddr4-evk # i.MX8MN DDR4 EVK Board
- fsl,imx8mn-evk # i.MX8MN LPDDR4 EVK Board
- gw,imx8mn-gw7902 # i.MX8MM Gateworks Board
- solidrun,solidsense-n8-compact # SolidRun SolidSense N8 Compact
- const: fsl,imx8mn
- description: ifm i.MX8MN VHIP4 based boards
@@ -1106,6 +1122,7 @@ properties:
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
- dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- emcraft,imx8mp-navqp # i.MX8MP Emcraft Systems NavQ+ Kit
- fsl,imx8mp-ab2 # i.MX8MP Audio Board V2
- fsl,imx8mp-evk # i.MX8MP EVK Board
- fsl,imx8mp-evk-revb4 # i.MX8MP EVK Rev B4 Board
- fsl,imx8mp-frdm # i.MX8MP Freedom Board
@@ -1225,6 +1242,7 @@ properties:
items:
- enum:
- solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M
- solidrun,imx8mp-hummingboard-iiot # SolidRun i.MX8MP SoM on HummingBoard IIoT
- solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate
- solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro
- solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse
@@ -1420,6 +1438,16 @@ properties:
- const: tq,imx8dxp-tqma8xdps # TQ-Systems GmbH TQMa8XDPS SOM
- const: fsl,imx8dxp
- description:
TQMa8x is a series of SOM featuring NXP i.MX8 system-on-chip
variants. It is designed to be clicked on different carrier boards
MBa8x is the starterkit
items:
- enum:
- tq,imx8qm-tqma8qm-mba8x # TQ-Systems GmbH TQMa8QM SOM on MBa8x
- const: tq,imx8qm-tqma8qm # TQ-Systems GmbH TQMa8QM SOM
- const: fsl,imx8qm
- description: i.MX8ULP based Boards
items:
- enum:
@@ -1432,6 +1460,7 @@ properties:
- enum:
- fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board
- fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board
- fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board
- const: fsl,imx91
- description: i.MX93 based Boards
@@ -1441,6 +1470,7 @@ properties:
- fsl,imx93-11x11-evk # i.MX93 11x11 EVK Board
- fsl,imx93-11x11-frdm # i.MX93 11x11 FRDM Board
- fsl,imx93-14x14-evk # i.MX93 14x14 EVK Board
- fsl,imx93-wireless-evk # i.MX93 and IW610G WLCSP (Wi-Fi + BLE + 802.15.4) SiP EVK Board
- const: fsl,imx93
- description: i.MX94 based Boards
@@ -1477,6 +1507,36 @@ properties:
- const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module
- const: fsl,imx95
- description: Toradex Boards with Verdin iMX95 Modules
items:
- enum:
- toradex,verdin-imx95-nonwifi-dahlia # Verdin iMX95 Module on Dahlia
- toradex,verdin-imx95-nonwifi-dev # Verdin iMX95 Module on Verdin Development Board
- toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy
- toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow
- toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia
- const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT
- const: toradex,verdin-imx95 # Verdin iMX95 Module
- const: fsl,imx95
- description: Toradex Boards with Verdin iMX95 Wi-Fi / BT Modules
items:
- enum:
- toradex,verdin-imx95-wifi-dahlia # Verdin iMX95 Wi-Fi / BT Module on Dahlia
- toradex,verdin-imx95-wifi-dev # Verdin iMX95 Wi-Fi / BT Module on Verdin Development B.
- toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy
- toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow
- toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia
- const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module
- const: toradex,verdin-imx95 # Verdin iMX95 Module
- const: fsl,imx95
- description: Variscite DART-MX95 based Boards
items:
- const: variscite,var-dart-mx95-sonata # Variscite DART-MX95 SOM on Sonata Development Board
- const: variscite,var-dart-mx95 # Variscite DART-MX95 SOM
- const: fsl,imx95
- description: i.MXRT1050 based Boards
items:
- enum:
@@ -1522,11 +1582,14 @@ properties:
soldered on an adapter board or for the connector variant
MBa93xxLA mainboard is a single board computer using the solderable
SOM variant
MBa93xxLA-MINI mainboard is a single board computer using the solderable
SOM variant
items:
- enum:
- tq,imx93-tqma9352-mba91xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa91xxCA
- tq,imx93-tqma9352-mba93xxca # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM on MBa93xxCA
- tq,imx93-tqma9352-mba93xxla # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA SBC
- tq,imx93-tqma9352-mba93xxla-mini # TQ-Systems GmbH i.MX93 TQMa93xxLA SOM on MBa93xxLA-MINI SBC
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
@@ -1545,6 +1608,12 @@ properties:
- const: phytec,imx93-phycore-som # phyCORE-i.MX93 SoM
- const: fsl,imx93
- description: Variscite DART-MX91 based boards
items:
- const: variscite,var-dart-mx91-sonata # Variscite DART-MX91 on Sonata Development Board
- const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM
- const: fsl,imx91
- description: Variscite VAR-SOM-MX93 based boards
items:
- const: variscite,var-som-mx93-symphony
@@ -1557,6 +1626,17 @@ properties:
- const: kontron,imx93-osm-s # Kontron OSM-S i.MX93 SoM
- const: fsl,imx93
- description:
TQMa95xxLA is a series of SOM featuring NXP i.MX95 SoC variants,
designed to be soldered on different carrier boards.
MBa95xxCA is a carrier reference design / starter kit that allows
to use TQMa95xxLA via an adaper board.
items:
- enum:
- tq,imx95-tqma9596la-mba95xxca # TQ-Systems GmbH i.MX95 TQMa95xxLA SOM on MBa95xxCA
- const: tq,imx95-tqma9596la # TQ-Systems GmbH i.MX95 TQMa95xxLA SOM
- const: fsl,imx95
- description:
TQMa95xxSA is a series of SOM featuring NXP i.MX95 SoC variants.
It has the SMARC form factor and is designed to be placed on
@@ -1827,6 +1907,12 @@ properties:
- fsl,s32v234-evb # S32V234-EVB2 Customer Evaluation Board
- const: fsl,s32v234
- description: S32N79 based Boards
items:
- enum:
- nxp,s32n79-rdb
- const: nxp,s32n79
- description: Traverse LS1088A based Boards
items:
- enum:
Bindings/arm/marvell/armada-7k-8k.yaml
+11
View File
@@ -21,6 +21,17 @@ properties:
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description:
Falcon (DB-98CX85x0) Development board COM Express Carrier plus
Armada 7020 SoC COM Express CPU module
items:
- const: marvell,armada7020-falcon-carrier
- const: marvell,db-falcon-carrier
- const: marvell,armada7020-cpu-module
- const: marvell,armada7020
- const: marvell,armada-ap806-dual
- const: marvell,armada-ap806
- description: Armada 7040 SoC
items:
- enum:
Bindings/arm/mediatek/mediatek,audsys.yaml
+29 -30
View File
@@ -49,38 +49,37 @@ required:
- '#clock-cells'
allOf:
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-audsys
- mediatek,mt7622-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
- if:
properties:
compatible:
contains:
enum:
- mediatek,mt2701-audsys
- mediatek,mt7622-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt2701-audio.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-audiosys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8192-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mt8192-afe-pcm.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8183-audiosys
then:
properties:
audio-controller:
$ref: /schemas/sound/mediatek,mt8183-audio.yaml#
- if:
properties:
compatible:
contains:
const: mediatek,mt8192-audsys
then:
properties:
audio-controller:
$ref: /schemas/sound/mt8192-afe-pcm.yaml#
additionalProperties: false
Bindings/arm/microchip,sam9x60-pit64b.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/microchip,sam9x60-pit64b.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PIT64B 64-bit Periodic Interval Timer
maintainers:
- Nicolas Ferre <[email protected]>
- Claudiu Beznea <[email protected]>
description:
The Microchip PIT64B is a 64-bit periodic interval timer used in
several modern Microchip ARM SoCs including SAM9X60, SAM9X7 and
SAMA7D65 families. It provides extended timing range, flexible
clock selection and supports both periodic and one-shot interrupt
generation modes.
properties:
compatible:
oneOf:
- const: microchip,sam9x60-pit64b
- items:
- enum:
- microchip,sam9x7-pit64b
- microchip,sama7d65-pit64b
- microchip,sama7g5-pit64b
- const: microchip,sam9x60-pit64b
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
items:
enum:
- pclk
- gclk
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/at91.h>
timer@f0028000 {
compatible = "microchip,sama7g5-pit64b", "microchip,sam9x60-pit64b";
reg = <0xf0028000 0x100>;
interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>;
clock-names = "pclk", "gclk";
};
...
Bindings/arm/microchip,sama7g5-chipid.yaml
+41
View File
@@ -0,0 +1,41 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/microchip,sama7g5-chipid.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Atmel/Microchip RAMC SDRAM/DDR Controller
maintainers:
- Nicolas Ferre <[email protected]>
- Claudiu Beznea <[email protected]>
description:
This binding describes the Atmel/Microchip Chip ID register block used
for SoC identification and revision information. It requires compatible
strings matching specific SoC families and a reg property defining the
register address and size.
properties:
compatible:
enum:
- atmel,sama5d2-chipid
- microchip,sama7d65-chipid
- microchip,sama7g5-chipid
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
chipid@fc069000 {
compatible = "atmel,sama5d2-chipid";
reg = <0xfc069000 0x8>;
};
...
Bindings/arm/nxp/lpc32xx.yaml
+22
View File
@@ -22,5 +22,27 @@ properties:
- phytec,phy3250
- const: nxp,lpc3250
- items:
- enum:
- ea,lpc4357-developers-kit
- const: nxp,lpc4357
- const: nxp,lpc4350
- items:
- enum:
- ciaa,lpc4337
- const: nxp,lpc4337
- const: nxp,lpc4350
- items:
- enum:
- hitex,lpc4350-eval-board
- const: nxp,lpc4350
- items:
- enum:
- myir,myd-lpc4357
- const: nxp,lpc4357
additionalProperties: true
...
Bindings/arm/qcom.yaml
+53
View File
@@ -61,6 +61,21 @@ properties:
- qcom,apq8084-sbc
- const: qcom,apq8084
- items:
- enum:
- qcom,eliza-mtp
- const: qcom,eliza
- items:
- enum:
- qcom,glymur-crd
- const: qcom,glymur
- items:
- enum:
- qcom,mahua-crd
- const: qcom,mahua
- items:
- enum:
- fairphone,fp6
@@ -171,6 +186,7 @@ properties:
- qcom,msm8916-mtp
- samsung,a3u-eur
- samsung,a5u-eur
- samsung,coreprimeltevzw
- samsung,e5
- samsung,e7
- samsung,fortuna3g
@@ -186,6 +202,7 @@ properties:
- samsung,serranove
- thwc,uf896
- thwc,ufi001c
- wiko,chuppito
- wingtech,wt86518
- wingtech,wt86528
- wingtech,wt88047
@@ -195,6 +212,8 @@ properties:
- items:
- enum:
- xiaomi,riva
- xiaomi,rolex
- xiaomi,tiare
- const: qcom,msm8917
- items:
@@ -243,6 +262,13 @@ properties:
- const: qcom,apq8096-sbc
- const: qcom,apq8096
- items:
- const: arrow,apq8096sg-db820c
- const: arrow,apq8096-db820c
- const: qcom,apq8096-sbc
- const: qcom,apq8096sg
- const: qcom,apq8096
- items:
- enum:
- oneplus,oneplus3
@@ -297,6 +323,11 @@ properties:
- tplink,archer-ax55-v1
- const: qcom,ipq5018
- items:
- enum:
- qcom,ipq5210-rdp504
- const: qcom,ipq5210
- items:
- enum:
- qcom,ipq5332-ap-mi01.2
@@ -326,8 +357,10 @@ properties:
- items:
- enum:
- qcom,ipq9574-ap-al02-c2
- qcom,ipq9574-ap-al02-c2-emmc
- qcom,ipq9574-ap-al02-c6
- qcom,ipq9574-ap-al02-c7
- qcom,ipq9574-ap-al02-c7-emmc
- qcom,ipq9574-ap-al02-c8
- qcom,ipq9574-ap-al02-c9
- const: qcom,ipq9574
@@ -360,6 +393,7 @@ properties:
- qcom,qcs6490-rb3gen2
- radxa,dragon-q6a
- shift,otter
- thundercomm,minipc-g1iot
- thundercomm,rubikpi3
- const: qcom,qcm6490
@@ -385,6 +419,7 @@ properties:
- items:
- enum:
- acer,aspire1
- ecs,liva-qc710
- qcom,sc7180-idp
- const: qcom,sc7180
@@ -844,6 +879,12 @@ properties:
- google,sargo
- const: qcom,sdm670
- items:
- enum:
- google,bonito-tianma
- const: google,bonito
- const: qcom,sdm670
- items:
- enum:
- qcom,sdx55-mtp
@@ -876,6 +917,7 @@ properties:
- items:
- enum:
- arduino,monza
- qcom,monaco-evk
- qcom,qcs8300-ride
- const: qcom,qcs8300
@@ -883,6 +925,7 @@ properties:
- items:
- enum:
- qcom,qcs615-ride
- qcom,talos-evk
- const: qcom,qcs615
- const: qcom,sm6150
@@ -966,6 +1009,7 @@ properties:
- sony,pdx201
- xiaomi,ginkgo
- xiaomi,laurel-sprout
- xiaomi,willow
- const: qcom,sm6125
- items:
@@ -1057,6 +1101,7 @@ properties:
- items:
- enum:
- ayaneo,pocket-s2
- qcom,sm8650-hdk
- qcom,sm8650-mtp
- qcom,sm8650-qrd
@@ -1104,6 +1149,7 @@ properties:
- dell,xps13-9345
- hp,elitebook-ultra-g1q
- hp,omnibook-x14
- lenovo,ideacentre-mini-01q8x10
- lenovo,yoga-slim7x
- microsoft,romulus13
- microsoft,romulus15
@@ -1122,6 +1168,12 @@ properties:
- const: microsoft,denali
- const: qcom,x1e80100
- items:
- enum:
- qcom,purwa-iot-evk
- const: qcom,purwa-iot-som
- const: qcom,x1p42100
- items:
- enum:
- asus,zenbook-a14-ux3407qa-lcd
@@ -1131,6 +1183,7 @@ properties:
- items:
- enum:
- asus,vivobook-s15-x1p4
- hp,omnibook-x14-fe1
- lenovo,thinkbook-16
- qcom,x1p42100-crd
Bindings/arm/rockchip.yaml
+19 -1
View File
@@ -754,6 +754,11 @@ properties:
- const: khadas,edge2
- const: rockchip,rk3588s
- description: Khadas Edge-2L series boards
items:
- const: khadas,edge-2l
- const: rockchip,rk3576
- description: Kobol Helios64
items:
- const: kobol,helios64
@@ -808,11 +813,22 @@ properties:
- const: netxeon,r89
- const: rockchip,rk3288
- description: Onion Omega4 Evaluation board
items:
- const: onion,omega4-evb
- const: onion,omega4
- const: rockchip,rv1103b
- description: OPEN AI LAB EAIDK-610
items:
- const: openailab,eaidk-610
- const: rockchip,rk3399
- description: OneThing Edge Cube series
items:
- const: onething,edge-cube
- const: rockchip,rk3566
- description: Xunlong Orange Pi RK3399 board
items:
- const: xunlong,rk3399-orangepi
@@ -1187,7 +1203,9 @@ properties:
- description: Rockchip RK3576 Evaluation board
items:
- const: rockchip,rk3576-evb1-v10
- enum:
- rockchip,rk3576-evb1-v10
- rockchip,rk3576-evb2-v10
- const: rockchip,rk3576
- description: Rockchip RK3588 Evaluation board
Bindings/arm/samsung/samsung-boards.yaml
+3
View File
@@ -117,6 +117,7 @@ properties:
- description: Exynos5250 based boards
items:
- enum:
- google,manta # Google Manta (Nexus 10)
- google,snow-rev5 # Google Snow Rev 5+
- google,spring # Google Spring
- insignal,arndale # Insignal Arndale
@@ -216,7 +217,9 @@ properties:
items:
- enum:
- samsung,a2corelte # Samsung Galaxy A2 Core
- samsung,j5y17lte # Samsung Galaxy J5 (2017)
- samsung,j6lte # Samsung Galaxy J6
- samsung,j7xelte # Samsung Galaxy J7 (2016)
- samsung,on7xelte # Samsung Galaxy J7 Prime
- const: samsung,exynos7870
Bindings/arm/stm32/stm32.yaml
+5 -3
View File
@@ -183,10 +183,12 @@ properties:
- const: seeed,stm32mp157c-odyssey-som
- const: st,stm32mp157
- description: Phytec STM32MP1 SoM based Boards
- description: Phytec STM32MP157 SoM based Boards
items:
- const: phytec,phycore-stm32mp1-3
- const: phytec,phycore-stm32mp157c-som
- enum:
- phytec,phycore-stm32mp1-3 # phyBOARD-Sargas with phyCORE-STM32MP157C SoM
- enum:
- phytec,phycore-stm32mp157c-som # phyCORE-STM32MP157C SoM
- const: st,stm32mp157
- description: Ultratronik STM32MP1 SBC based Boards
Bindings/arm/sunxi.yaml
+5
View File
@@ -901,6 +901,11 @@ properties:
- const: allwinner,sl631
- const: allwinner,sun8i-v3
- description: TaiqiCat A01
items:
- const: ultrapower,taiqicat-a01
- const: allwinner,sun50i-h6
- description: Tanix TX1
items:
- const: oranth,tanix-tx1
Bindings/arm/tegra.yaml
+53 -3
View File
@@ -131,6 +131,33 @@ properties:
- const: toradex,apalis-tk1-v1.2
- const: toradex,apalis-tk1
- const: nvidia,tegra124
- items:
- const: google,nyan-big-rev7
- const: google,nyan-big-rev6
- const: google,nyan-big-rev5
- const: google,nyan-big-rev4
- const: google,nyan-big-rev3
- const: google,nyan-big-rev2
- const: google,nyan-big-rev1
- const: google,nyan-big-rev0
- const: google,nyan-big
- const: google,nyan
- const: nvidia,tegra124
- items:
- const: google,nyan-blaze-rev10
- const: google,nyan-blaze-rev9
- const: google,nyan-blaze-rev8
- const: google,nyan-blaze-rev7
- const: google,nyan-blaze-rev6
- const: google,nyan-blaze-rev5
- const: google,nyan-blaze-rev4
- const: google,nyan-blaze-rev3
- const: google,nyan-blaze-rev2
- const: google,nyan-blaze-rev1
- const: google,nyan-blaze-rev0
- const: google,nyan-blaze
- const: google,nyan
- const: nvidia,tegra124
- items:
- enum:
- nvidia,norrin
@@ -184,17 +211,35 @@ properties:
- const: nvidia,tegra124
- items:
- enum:
- nvidia,darcy
- nvidia,p2371-0000
- nvidia,p2371-2180
- nvidia,p2571
- nvidia,p2894-0050-a08
- nvidia,p3450-0000
- const: nvidia,tegra210
- items:
- const: nvidia,p3541-0000
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: NVIDIA Jetson Nano
items:
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: NVIDIA Shield TV
items:
- const: nvidia,p2894-0050-a08
- const: nvidia,darcy
- const: nvidia,tegra210
- description: Google Pixel C
items:
- const: google,smaug-rev8
- const: google,smaug-rev7
- const: google,smaug-rev6
- const: google,smaug-rev5
- const: google,smaug-rev4
- const: google,smaug-rev3
- const: google,smaug-rev2
- const: google,smaug-rev1
- const: google,smaug
- const: nvidia,tegra210
- description: Jetson TX2 Developer Kit
items:
- const: nvidia,p2771-0000
@@ -268,5 +313,10 @@ properties:
- const: nvidia,p3971-0089+p3834-0008
- const: nvidia,p3834-0008
- const: nvidia,tegra264
- description: Jetson AGX Thor Developer Kit
items:
- const: nvidia,p4071-0000+p3834-0008
- const: nvidia,p3834-0008
- const: nvidia,tegra264
additionalProperties: true
Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
+1
View File
@@ -24,6 +24,7 @@ properties:
enum:
- nvidia,tegra186-ccplex-cluster
- nvidia,tegra234-ccplex-cluster
- nvidia,tegra238-ccplex-cluster
reg:
maxItems: 1
Bindings/arm/tegra/nvidia,tegra234-cbb.yaml
+4
View File
@@ -48,6 +48,10 @@ properties:
- nvidia,tegra234-dce-fabric
- nvidia,tegra234-rce-fabric
- nvidia,tegra234-sce-fabric
- nvidia,tegra238-ape-fabric
- nvidia,tegra238-aon-fabric
- nvidia,tegra238-bpmp-fabric
- nvidia,tegra238-cbb-fabric
reg:
maxItems: 1
Bindings/arm/ti/k3.yaml
+4 -1
View File
@@ -79,6 +79,7 @@ properties:
- toradex,verdin-am62-nonwifi-ivy # Verdin AM62 Module on Ivy
- toradex,verdin-am62-nonwifi-mallow # Verdin AM62 Module on Mallow
- toradex,verdin-am62-nonwifi-yavia # Verdin AM62 Module on Yavia
- toradex,verdin-am62-nonwifi-zinnia # Verdin AM62 Module on Zinnia
- const: toradex,verdin-am62-nonwifi # Verdin AM62 Module without Wi-Fi / BT
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
@@ -91,6 +92,7 @@ properties:
- toradex,verdin-am62-wifi-ivy # Verdin AM62 Wi-Fi / BT Module on Ivy
- toradex,verdin-am62-wifi-mallow # Verdin AM62 Wi-Fi / BT Module on Mallow
- toradex,verdin-am62-wifi-yavia # Verdin AM62 Wi-Fi / BT Module on Yavia
- toradex,verdin-am62-wifi-zinnia # Verdin AM62 Wi-Fi / BT Module on Zinnia
- const: toradex,verdin-am62-wifi # Verdin AM62 Wi-Fi / BT Module
- const: toradex,verdin-am62 # Verdin AM62 Module
- const: ti,am625
@@ -103,6 +105,7 @@ properties:
- toradex,verdin-am62p-nonwifi-ivy # Verdin AM62P Module on Ivy
- toradex,verdin-am62p-nonwifi-mallow # Verdin AM62P Module on Mallow
- toradex,verdin-am62p-nonwifi-yavia # Verdin AM62P Module on Yavia
- toradex,verdin-am62p-nonwifi-zinnia # Verdin AM62P Module on Zinnia
- const: toradex,verdin-am62p-nonwifi # Verdin AM62P Module without Wi-Fi / BT
- const: toradex,verdin-am62p # Verdin AM62P Module
- const: ti,am62p5
@@ -115,6 +118,7 @@ properties:
- toradex,verdin-am62p-wifi-ivy # Verdin AM62P Wi-Fi / BT Module on Ivy
- toradex,verdin-am62p-wifi-mallow # Verdin AM62P Wi-Fi / BT Module on Mallow
- toradex,verdin-am62p-wifi-yavia # Verdin AM62P Wi-Fi / BT Module on Yavia
- toradex,verdin-am62p-wifi-zinnia # Verdin AM62P Wi-Fi / BT Module on Zinnia
- const: toradex,verdin-am62p-wifi # Verdin AM62P Wi-Fi / BT Module
- const: toradex,verdin-am62p # Verdin AM62P Module
- const: ti,am62p5
@@ -208,7 +212,6 @@ properties:
items:
- enum:
- beagle,am67a-beagley-ai
- kontron,sa67 # Kontron SMARC-sAM67 board
- ti,j722s-evm
- const: ti,j722s
Bindings/arm/ti/omap.yaml
+2
View File
@@ -144,6 +144,8 @@ properties:
- motorola,droid-bionic # Motorola Droid Bionic XT875
- motorola,xyboard-mz609
- motorola,xyboard-mz617
- samsung,espresso7
- samsung,espresso10
- ti,omap4-panda
- ti,omap4-sdp
- const: ti,omap4430
Bindings/auxdisplay/holtek,ht16k33.yaml
+2 -3
View File
@@ -10,6 +10,7 @@ maintainers:
- Robin van der Gracht <[email protected]>
allOf:
- $ref: /schemas/input/input.yaml#
- $ref: /schemas/input/matrix-keymap.yaml#
properties:
@@ -33,9 +34,7 @@ properties:
interrupts:
maxItems: 1
debounce-delay-ms:
maxItems: 1
description: Debouncing interval time in milliseconds
debounce-delay-ms: true
linux,keymap: true
Bindings/bus/st,stm32mp131-dbg-bus.yaml
+76
View File
@@ -0,0 +1,76 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/st,stm32mp131-dbg-bus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STM32 Coresight bus
maintainers:
- Gatien Chevallier <[email protected]>
description:
The STM32 debug bus is in charge of checking the debug configuration
of the platform before probing the peripheral drivers that rely on the debug
domain.
properties:
compatible:
items:
- enum:
- st,stm32mp131-dbg-bus
- st,stm32mp151-dbg-bus
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges:
minItems: 1
maxItems: 2
"#access-controller-cells":
const: 1
description:
Contains the debug profile necessary to access the peripheral.
patternProperties:
"@[0-9a-f]+$":
description: Debug related peripherals
type: object
additionalProperties: true
required:
- access-controllers
required:
- "#access-controller-cells"
- "#address-cells"
- "#size-cells"
- compatible
- ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/stm32mp1-clks.h>
dbg_bus: bus@50080000 {
compatible = "st,stm32mp131-dbg-bus";
#address-cells = <1>;
#size-cells = <1>;
#access-controller-cells = <1>;
ranges = <0x50080000 0x50080000 0x3f80000>;
cti@50094000 {
compatible = "arm,coresight-cti", "arm,primecell";
reg = <0x50094000 0x1000>;
clocks = <&rcc CK_DBG>;
clock-names = "apb_pclk";
access-controllers = <&dbg_bus 0>;
};
};
Bindings/cache/qcom,llcc.yaml
Vendored
+2
View File
@@ -33,6 +33,7 @@ properties:
- qcom,sc7280-llcc
- qcom,sc8180x-llcc
- qcom,sc8280xp-llcc
- qcom,sdm670-llcc
- qcom,sdm845-llcc
- qcom,sm6350-llcc
- qcom,sm7150-llcc
@@ -204,6 +205,7 @@ allOf:
contains:
enum:
- qcom,sc7280-llcc
- qcom,sdm670-llcc
then:
properties:
reg:
Bindings/chrome/google,cros-ec-typec.yaml
+15 -4
View File
@@ -8,17 +8,28 @@ title: Google Chrome OS EC(Embedded Controller) Type C port driver.
maintainers:
- Benson Leung <[email protected]>
- Prashant Malani <pmalani@chromium.org>
- Abhishek Pandit-Subedi <abhishekpandit@chromium.org>
- Andrei Kuchynski <[email protected]>
- Łukasz Bartosik <[email protected]>
- Jameson Thies <[email protected]>
description:
Chrome OS devices have an Embedded Controller(EC) which has access to
Type C port state. This node is intended to allow the host to read and
control the Type C ports. The node for this device should be under a
cros-ec node like google,cros-ec-spi.
control the Type C ports. This binding is compatible with both the
cros-ec-typec and cros-ec-ucsi drivers. The cros-ec-typec driver
supports the host command interface used by the Chrome OS EC with a
built-in Type-C port manager and external Type-C Port Controller
(TCPC). The cros-ec-ucsi driver supports the USB Type-C Connector
System Software (UCSI) interface used by the Chrome OS EC when the
platform has a separate power delivery controller (PDC). The node for
this device should be under a cros-ec node like google,cros-ec-spi.
properties:
compatible:
const: google,cros-ec-typec
enum:
- google,cros-ec-typec
- google,cros-ec-ucsi
'#address-cells':
const: 1
Bindings/clock/airoha,en7523-scu.yaml
+5 -1
View File
@@ -32,6 +32,7 @@ properties:
- enum:
- airoha,en7523-scu
- airoha,en7581-scu
- econet,en751221-scu
reg:
items:
@@ -67,7 +68,9 @@ allOf:
- if:
properties:
compatible:
const: airoha,en7581-scu
enum:
- airoha,en7581-scu
- econet,en751221-scu
then:
properties:
reg:
@@ -98,3 +101,4 @@ examples:
#reset-cells = <1>;
};
};
Bindings/clock/axis,artpec9-clock.yaml
+232
View File
@@ -0,0 +1,232 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/axis,artpec9-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Axis ARTPEC-9 SoC clock controller
maintainers:
- Jesper Nilsson <[email protected]>
description: |
ARTPEC-9 clock controller is comprised of several CMU (Clock Management Unit)
units, generating clocks for different domains. Those CMU units are modeled
as separate device tree nodes, and might depend on each other.
The root clock in that root tree is an external clock: OSCCLK (25 MHz).
This external clock must be defined as a fixed-rate clock in dts.
CMU_CMU is a top-level CMU, where all base clocks are prepared using PLLs and
dividers, all other clocks of function blocks (other CMUs) are usually
derived from CMU_CMU.
Each clock is assigned an identifier and client nodes can use this identifier
to specify the clock which they consume. All clocks available for usage
in clock consumer nodes are defined as preprocessor macros in
'include/dt-bindings/clock/axis,artpec9-clk.h' header.
properties:
compatible:
enum:
- axis,artpec9-cmu-cmu
- axis,artpec9-cmu-bus
- axis,artpec9-cmu-core
- axis,artpec9-cmu-cpucl
- axis,artpec9-cmu-fsys0
- axis,artpec9-cmu-fsys1
- axis,artpec9-cmu-imem
- axis,artpec9-cmu-peri
reg:
maxItems: 1
clocks:
minItems: 1
maxItems: 5
clock-names:
minItems: 1
maxItems: 5
"#clock-cells":
const: 1
required:
- compatible
- reg
- clocks
- clock-names
- "#clock-cells"
allOf:
- if:
properties:
compatible:
const: axis,artpec9-cmu-cmu
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
clock-names:
items:
- const: fin_pll
- if:
properties:
compatible:
const: axis,artpec9-cmu-bus
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_BUS bus clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: bus
- if:
properties:
compatible:
const: axis,artpec9-cmu-core
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CORE main clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: main
- if:
properties:
compatible:
const: axis,artpec9-cmu-cpucl
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_CPUCL switch clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: switch
- if:
properties:
compatible:
const: axis,artpec9-cmu-fsys0
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_FSYS0 bus clock (from CMU_CMU)
- description: CMU_FSYS0 IP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: bus
- const: ip
- if:
properties:
compatible:
const: axis,artpec9-cmu-fsys1
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_FSYS1 scan0 clock (from CMU_CMU)
- description: CMU_FSYS1 scan1 clock (from CMU_CMU)
- description: CMU_FSYS1 bus clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: scan0
- const: scan1
- const: bus
- if:
properties:
compatible:
const: axis,artpec9-cmu-imem
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_IMEM ACLK clock (from CMU_CMU)
- description: CMU_IMEM CA5 clock (from CMU_CMU)
- description: CMU_IMEM JPEG clock (from CMU_CMU)
- description: CMU_IMEM SSS clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: aclk
- const: ca5
- const: jpeg
- const: sss
- if:
properties:
compatible:
const: axis,artpec9-cmu-peri
then:
properties:
clocks:
items:
- description: External reference clock (25 MHz)
- description: CMU_PERI IP clock (from CMU_CMU)
- description: CMU_PERI DISP clock (from CMU_CMU)
clock-names:
items:
- const: fin_pll
- const: ip
- const: disp
additionalProperties: false
examples:
# Clock controller node for CMU_FSYS1
- |
#include <dt-bindings/clock/axis,artpec9-clk.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
cmu_fsys1: clock-controller@14c10000 {
compatible = "axis,artpec9-cmu-fsys1";
reg = <0x0 0x14c10000 0x0 0x4000>;
#clock-cells = <1>;
clocks = <&fin_pll>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN0>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_SCAN1>,
<&cmu_cmu CLK_DOUT_CMU_FSYS1_BUS>;
clock-names = "fin_pll", "scan0", "scan1", "bus";
};
};
...
Bindings/clock/eswin,eic7700-clock.yaml
+46
View File
@@ -0,0 +1,46 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin EIC7700 SoC clock controller
maintainers:
- Yifeng Huang <[email protected]>
- Xuyang Dong <[email protected]>
description:
The clock controller generates and supplies clock to all the modules
for eic7700 SoC.
properties:
compatible:
const: eswin,eic7700-clock
reg:
maxItems: 1
clocks:
items:
- description: External 24MHz oscillator clock
'#clock-cells':
const: 1
required:
- compatible
- reg
- clocks
- '#clock-cells'
additionalProperties: false
examples:
- |
clock-controller@51828000 {
compatible = "eswin,eic7700-clock";
reg = <0x51828000 0x300>;
clocks = <&xtal24m>;
#clock-cells = <1>;
};
Bindings/clock/fsl,sai-clock.yaml
+36 -7
View File
@@ -10,10 +10,10 @@ maintainers:
- Michael Walle <[email protected]>
description: |
It is possible to use the BCLK pin of a SAI module as a generic clock
output. Some SoC are very constrained in their pin multiplexer
configuration. Eg. pins can only be changed groups. For example, on the
LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
It is possible to use the BCLK or MCLK pin of a SAI module as a generic
clock output. Some SoC are very constrained in their pin multiplexer
configuration. E.g. pins can only be changed in groups. For example, on
the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
the second pins are wasted. Using this binding it is possible to use the
clock of the second SAI as a MCLK clock for an audio codec, for example.
@@ -21,16 +21,45 @@ description: |
properties:
compatible:
const: fsl,vf610-sai-clock
oneOf:
- items:
- enum:
- fsl,imx8mm-sai-clock
- fsl,imx8mn-sai-clock
- fsl,imx8mp-sai-clock
- const: fsl,imx8mq-sai-clock
- items:
- enum:
- fsl,imx8mq-sai-clock
- fsl,vf610-sai-clock
reg:
maxItems: 1
clocks:
maxItems: 1
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: bus
- const: mclk1
'#clock-cells':
const: 0
maximum: 1
allOf:
- if:
properties:
compatible:
contains:
const: fsl,vf610-sai-clock
then:
properties:
clocks:
maxItems: 1
clock-names: false
required:
- compatible
Bindings/clock/imx6q-clock.yaml
+4
View File
@@ -29,20 +29,24 @@ properties:
const: 1
clocks:
minItems: 5
items:
- description: 24m osc
- description: 32k osc
- description: ckih1 clock input
- description: anaclk1 clock input
- description: anaclk2 clock input
- description: clock input from enet ref pad
clock-names:
minItems: 5
items:
- const: osc
- const: ckil
- const: ckih1
- const: anaclk1
- const: anaclk2
- const: enet_ref_pad
fsl,pmic-stby-poweroff:
$ref: /schemas/types.yaml#/definitions/flag
Bindings/clock/imx6ul-clock.yaml
+4
View File
@@ -29,18 +29,22 @@ properties:
const: 1
clocks:
minItems: 4
items:
- description: 32k osc
- description: 24m osc
- description: ipp_di0 clock input
- description: ipp_di1 clock input
- description: clock input from enet1 ref pad
clock-names:
minItems: 4
items:
- const: ckil
- const: osc
- const: ipp_di0
- const: ipp_di1
- const: enet1_ref_pad
required:
- compatible
Bindings/clock/nvidia,tegra124-dfll.yaml
+290
View File
@@ -0,0 +1,290 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/nvidia,tegra124-dfll.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra124 (and later) DFLL FCPU clocksource
maintainers:
- Thierry Reding <[email protected]>
- Jon Hunter <[email protected]>
description:
The DFLL IP block on Tegra is a root clocksource designed for clocking
the fast CPU cluster. It consists of a free-running voltage controlled
oscillator connected to the CPU voltage rail (VDD_CPU), and a closed
loop control module that will automatically adjust the VDD_CPU voltage
by communicating with an off-chip PMIC either via an I2C bus or via
PWM signals.
properties:
compatible:
enum:
- nvidia,tegra124-dfll
- nvidia,tegra210-dfll
reg:
items:
- description: DFLL control logic
- description: I2C output logic
- description: Integrated I2C controller
- description: Look-up table RAM for voltage register values
interrupts:
maxItems: 1
"#clock-cells":
const: 0
clocks:
items:
- description: Clock source for the DFLL control logic
- description: Closed loop reference clock
- description: Clock source for the integrated I2C controller
clock-names:
items:
- const: soc
- const: ref
- const: i2c
clock-output-names:
description: Name of the clock output
items:
- const: dfllCPU_out
resets:
minItems: 1
maxItems: 2
reset-names:
minItems: 1
items:
- const: dvco
- const: dfll
vdd-cpu-supply:
description: Regulator for the CPU voltage rail that the DFLL
hardware will start controlling. The regulator will be queried for
the I2C register, control values and supported voltages.
nvidia,sample-rate:
description: Sample rate of the DFLL control loop
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 12500
maximum: 25000
nvidia,droop-ctrl:
description: Droop control parameter (CL_DVFS_DROOP_CTRL) in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
nvidia,force-mode:
description: See the field DFLL_PARAMS_FORCE_MODE in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
oneOf:
- description: disabled
const: 0
- description: fixed delay mode
const: 1
- description: auto mode
const: 2
nvidia,cf:
description: Numeric value, see the field DFLL_PARAMS_CF_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 63
nvidia,ci:
description: Numeric value, see the field DFLL_PARAMS_CI_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 7
nvidia,cg:
description: Numeric value, see the field DFLL_PARAMS_CG_PARAM in the TRM
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
# optional properties
nvidia,cg-scale:
description: Boolean value, see the field DFLL_PARAMS_CG_SCALE in the TRM
$ref: /schemas/types.yaml#/definitions/flag
nvidia,pwm-to-pmic:
description: Use PWM to control regulator rather than I2C
$ref: /schemas/types.yaml#/definitions/flag
nvidia,i2c-fs-rate:
description: I2C transfer rate, if using full speed mode
$ref: /schemas/types.yaml#/definitions/uint32
enum: [100000, 400000]
# required properties for PWM mode
nvidia,pwm-period-nanoseconds:
description: Period of PWM square wave in nanoseconds
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 1000
maximum: 1000000000
nvidia,pwm-tristate-microvolts:
description: Regulator voltage in microvolts when PWM control is disabled
and the PWM output is tristated. Note that this voltage is configured in
hardware, typically via a resistor divider.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
nvidia,pwm-min-microvolts:
description: Regulator voltage in microvolts when PWM control is enabled
and PWM output is low. Hence, this is the minimum output voltage that
the regulator supports when PWM control is enabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
nvidia,pwm-voltage-step-microvolts:
description: |
Voltage increase in micro volts corresponding to a 1/33th increase
in duty cycle. For example, the voltage for 2/33th duty cycle would be:
nvidia,pwm-min-microvolts + nvidia,pwm-voltage-step-microvolts * 2
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 100000
pinctrl-0:
description: I/O pad configuration when PWM control is enabled
pinctrl-1:
description: I/O pad configuration when PWM control is disabled
pinctrl-names:
items:
- const: dvfs_pwm_enable
- const: dvfs_pwm_disable
required:
- compatible
- reg
- interrupts
- "#clock-cells"
- clocks
- clock-names
- clock-output-names
- resets
- reset-names
- nvidia,sample-rate
- nvidia,droop-ctrl
- nvidia,force-mode
- nvidia,cf
- nvidia,ci
- nvidia,cg
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: nvidia,tegra124-dfll
then:
properties:
resets:
maxItems: 1
reset-names:
maxItems: 1
else:
properties:
resets:
minItems: 2
reset-names:
minItems: 2
- if:
required:
- nvidia,pwm-to-pmic
then:
required:
- nvidia,pwm-min-microvolts
- nvidia,pwm-period-nanoseconds
- nvidia,pwm-tristate-microvolts
- nvidia,pwm-voltage-step-microvolts
else:
required:
- vdd-cpu-supply
examples:
- |
#include <dt-bindings/clock/tegra124-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra124-car.h>
clock@70110000 {
compatible = "nvidia,tegra124-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
<0x70110000 0x100>, /* I2C output control */
<0x70110100 0x100>, /* Integrated I2C controller */
<0x70110200 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA124_CLK_DFLL_SOC>,
<&tegra_car TEGRA124_CLK_DFLL_REF>,
<&tegra_car TEGRA124_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA124_RST_DFLL_DVCO>;
reset-names = "dvco";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,sample-rate = <12500>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <10>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,i2c-fs-rate = <400000>;
};
- |
#include <dt-bindings/clock/tegra210-car.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/tegra210-car.h>
clock@70110000 {
compatible = "nvidia,tegra210-dfll";
reg = <0x70110000 0x100>, /* DFLL control */
<0x70110000 0x100>, /* I2C output control */
<0x70110100 0x100>, /* Integrated I2C controller */
<0x70110200 0x100>; /* Look-up table RAM */
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&tegra_car TEGRA210_CLK_DFLL_SOC>,
<&tegra_car TEGRA210_CLK_DFLL_REF>,
<&tegra_car TEGRA210_CLK_I2C5>;
clock-names = "soc", "ref", "i2c";
resets = <&tegra_car TEGRA210_RST_DFLL_DVCO>,
<&tegra_car 155>;
reset-names = "dvco", "dfll";
#clock-cells = <0>;
clock-output-names = "dfllCPU_out";
vdd-cpu-supply = <&vdd_cpu>;
nvidia,sample-rate = <25000>;
nvidia,droop-ctrl = <0x00000f00>;
nvidia,force-mode = <1>;
nvidia,cf = <6>;
nvidia,ci = <0>;
nvidia,cg = <2>;
nvidia,pwm-min-microvolts = <708000>; /* 708mV */
nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
nvidia,pwm-to-pmic;
nvidia,pwm-tristate-microvolts = <1000000>;
nvidia,pwm-voltage-step-microvolts = <19200>; /* 19.2mV */
};
Bindings/clock/qcom,eliza-dispcc.yaml
+96
View File
@@ -0,0 +1,96 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Display Clock & Reset Controller for Qualcomm Eliza SoC
maintainers:
- Bjorn Andersson <[email protected]>
- Konrad Dybcio <[email protected]>
- Krzysztof Kozlowski <[email protected]>
description: |
Display clock control module provides the clocks, resets and power
domains on Qualcomm Eliza SoC platform.
See also:
- include/dt-bindings/clock/qcom,eliza-dispcc.h
properties:
compatible:
enum:
- qcom,eliza-dispcc
clocks:
items:
- description: Board XO source
- description: Board Always On XO source
- description: Display's AHB clock
- description: sleep clock
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
- description: Pixel clock from DSI PHY1
- description: Link clock from DP PHY0
- description: VCO DIV clock from DP PHY0
- description: Link clock from DP PHY1
- description: VCO DIV clock from DP PHY1
- description: Link clock from DP PHY2
- description: VCO DIV clock from DP PHY2
- description: Link clock from DP PHY3
- description: VCO DIV clock from DP PHY3
- description: HDMI link clock from HDMI PHY
power-domains:
maxItems: 1
required-opps:
maxItems: 1
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,eliza-gcc.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@af00000 {
compatible = "qcom,eliza-dispcc";
reg = <0x0af00000 0x20000>;
clocks = <&bi_tcxo_div2>,
<&bi_tcxo_ao_div2>,
<&gcc GCC_DISP_AHB_CLK>,
<&sleep_clk>,
<&dsi0_phy DSI_BYTE_PLL_CLK>,
<&dsi0_phy DSI_PIXEL_PLL_CLK>,
<&dsi1_phy DSI_BYTE_PLL_CLK>,
<&dsi1_phy DSI_PIXEL_PLL_CLK>,
<&dp0_phy 0>,
<&dp0_phy 1>,
<&dp1_phy 0>,
<&dp1_phy 1>,
<&dp2_phy 0>,
<&dp2_phy 1>,
<&dp3_phy 0>,
<&dp3_phy 1>,
<&hdmi_phy>;
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
required-opps = <&rpmhpd_opp_low_svs>;
};
...
Bindings/clock/qcom,glymur-dispcc.yaml
+2 -2
View File
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Display Clock & Reset Controller on GLYMUR
title: Qualcomm Display Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <[email protected]>
description: |
Qualcomm display clock control module which supports the clocks, resets and
power domains for the MDSS instances on GLYMUR SoC.
power domains for the MDSS instances on Glymur SoC.
See also:
include/dt-bindings/clock/qcom,dispcc-glymur.h
Bindings/clock/qcom,ipq5210-gcc.yaml
+62
View File
@@ -0,0 +1,62 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,ipq5210-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on IPQ5210
maintainers:
- Bjorn Andersson <[email protected]>
- Kathiravan Thirumoorthy <[email protected]>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on IPQ5210
See also:
include/dt-bindings/clock/qcom,ipq5210-gcc.h
include/dt-bindings/reset/qcom,ipq5210-gcc.h
properties:
compatible:
const: qcom,ipq5210-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE30 PHY0 pipe clock source
- description: PCIE30 PHY1 pipe clock source
- description: USB3 PHY pipe clock source
- description: NSS common clock source
'#power-domain-cells': false
'#interconnect-cells':
const: 1
required:
- compatible
- clocks
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
clock-controller@1800000 {
compatible = "qcom,ipq5210-gcc";
reg = <0x01800000 0x40000>;
clocks = <&xo_board_clk>,
<&sleep_clk>,
<&pcie30_phy0_pipe_clk>,
<&pcie30_phy1_pipe_clk>,
<&usb3phy_0_cc_pipe_clk>,
<&nss_cmn_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
};
...
Bindings/clock/qcom,ipq9574-cmn-pll.yaml
+2
View File
@@ -26,6 +26,8 @@ properties:
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5424-cmn-pll
- qcom,ipq6018-cmn-pll
- qcom,ipq8074-cmn-pll
- qcom,ipq9574-cmn-pll
reg:
Bindings/clock/qcom,kaanapali-gxclkctl.yaml
+2
View File
@@ -20,7 +20,9 @@ description: |
properties:
compatible:
enum:
- qcom,glymur-gxclkctl
- qcom,kaanapali-gxclkctl
- qcom,sm8750-gxclkctl
power-domains:
description:
Bindings/clock/qcom,milos-gcc.yaml
+14 -2
View File
@@ -8,16 +8,21 @@ title: Qualcomm Global Clock & Reset Controller on Milos
maintainers:
- Luca Weiss <[email protected]>
- Taniya Das <[email protected]>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Milos.
See also: include/dt-bindings/clock/qcom,milos-gcc.h
See also:
- include/dt-bindings/clock/qcom,eliza-gcc.h
- include/dt-bindings/clock/qcom,milos-gcc.h
properties:
compatible:
const: qcom,milos-gcc
enum:
- qcom,eliza-gcc
- qcom,milos-gcc
clocks:
items:
@@ -30,9 +35,14 @@ properties:
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
power-domains:
items:
- description: CX domain
required:
- compatible
- clocks
- power-domains
- '#power-domain-cells'
allOf:
@@ -43,6 +53,7 @@ unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,milos-gcc";
reg = <0x00100000 0x1f4200>;
@@ -54,6 +65,7 @@ examples:
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
Bindings/clock/qcom,nord-gcc.yaml
+58
View File
@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global Clock & Reset Controller on Nord SoC
maintainers:
- Taniya Das <[email protected]>
description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on Nord SoC.
See also: include/dt-bindings/clock/qcom,nord-gcc.h
properties:
compatible:
const: qcom,nord-gcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: PCIE A Pipe clock source
- description: PCIE B Pipe clock source
- description: PCIE C Pipe clock source
- description: PCIE D Pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@100000 {
compatible = "qcom,nord-gcc";
reg = <0x00100000 0x1f4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&pcie_a_pipe_clk>,
<&pcie_b_pipe_clk>,
<&pcie_c_pipe_clk>,
<&pcie_d_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,nord-negcc.yaml
+60
View File
@@ -0,0 +1,60 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
maintainers:
- Taniya Das <[email protected]>
description: |
Qualcomm global clock control (NE) module provides the clocks, resets
and power domains on Nord SoC.
See also: include/dt-bindings/clock/qcom,nord-negcc.h
properties:
compatible:
const: qcom,nord-negcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
- description: UFS Phy Rx symbol 0 clock source
- description: UFS Phy Rx symbol 1 clock source
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy sec wrapper pipe clock source
- description: USB3 Phy wrapper pipe clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@8900000 {
compatible = "qcom,nord-negcc";
reg = <0x08900000 0xf4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>,
<&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>,
<&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_sec_pipe_clk>,
<&usb3_phy_pipe_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,nord-nwgcc.yaml
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Global North West and South East Clock & Reset Controller
on Nord SoC
maintainers:
- Taniya Das <[email protected]>
description: |
Qualcomm global clock control (NW, SE) module provides the clocks, resets
and power domains on Nord SoC.
See also:
include/dt-bindings/clock/qcom,nord-nwgcc.h
include/dt-bindings/clock/qcom,nord-segcc.h
properties:
compatible:
enum:
- qcom,nord-nwgcc
- qcom,nord-segcc
clocks:
items:
- description: Board XO source
- description: Sleep clock source
required:
- compatible
- clocks
- '#power-domain-cells'
allOf:
- $ref: qcom,gcc.yaml#
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
clock-controller@8b00000 {
compatible = "qcom,nord-nwgcc";
reg = <0x08b00000 0xf4200>;
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&sleep_clk>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
};
...
Bindings/clock/qcom,rpmhcc.yaml
+2
View File
@@ -17,9 +17,11 @@ description: |
properties:
compatible:
enum:
- qcom,eliza-rpmh-clk
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
Bindings/clock/qcom,sm8450-gpucc.yaml
+26 -1
View File
@@ -8,12 +8,14 @@ title: Qualcomm Graphics Clock & Reset Controller on SM8450
maintainers:
- Konrad Dybcio <[email protected]>
- Taniya Das <[email protected]>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
See also::
See also:
include/dt-bindings/clock/qcom,glymur-gpucc.h
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
@@ -22,11 +24,13 @@ description: |
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
include/dt-bindings/reset/qcom,sm8750-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
enum:
- qcom,glymur-gpucc
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,sar2130p-gpucc
@@ -35,6 +39,7 @@ properties:
- qcom,sm8475-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
- qcom,sm8750-gpucc
- qcom,x1e80100-gpucc
- qcom,x1p42100-gpucc
@@ -44,6 +49,16 @@ properties:
- description: GPLL0 main branch source
- description: GPLL0 div branch source
power-domains:
items:
- description: A phandle to the MX power-domain
- description: A phandle to the CX power-domain
required-opps:
items:
- description: A phandle to an OPP node describing MX performance points
- description: A phandle to an OPP node describing CX performance points
required:
- compatible
- clocks
@@ -51,6 +66,16 @@ required:
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8750-gpucc
then:
required:
- power-domains
- required-opps
unevaluatedProperties: false
Bindings/clock/qcom,sm8450-videocc.yaml
+3
View File
@@ -15,6 +15,7 @@ description: |
domains on SM8450.
See also:
include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -23,6 +24,7 @@ description: |
properties:
compatible:
enum:
- qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
@@ -63,6 +65,7 @@ allOf:
compatible:
contains:
enum:
- qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
Bindings/clock/qcom,sm8550-tcsr.yaml
+4
View File
@@ -15,7 +15,9 @@ description: |
power domains on SM8550
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
- include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -24,9 +26,11 @@ properties:
compatible:
items:
- enum:
- qcom,eliza-tcsr
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
Bindings/clock/renesas,rzg2l-cpg.yaml
+35 -5
View File
@@ -28,19 +28,30 @@ properties:
- renesas,r9a07g044-cpg # RZ/G2{L,LC}
- renesas,r9a07g054-cpg # RZ/V2L
- renesas,r9a08g045-cpg # RZ/G3S
- renesas,r9a08g046-cpg # RZ/G3L
- renesas,r9a09g011-cpg # RZ/V2M
reg:
maxItems: 1
clocks:
maxItems: 1
minItems: 1
items:
- description: Clock source to CPG can be either from external clock
input (EXCLK) or crystal oscillator (XIN/XOUT).
- description: ETH0 TXC clock input
- description: ETH0 RXC clock input
- description: ETH1 TXC clock input
- description: ETH1 RXC clock input
clock-names:
description:
Clock source to CPG can be either from external clock input (EXCLK) or
crystal oscillator (XIN/XOUT).
const: extal
minItems: 1
items:
- const: extal
- const: eth0_txc_tx_clk
- const: eth0_rxc_rx_clk
- const: eth1_txc_tx_clk
- const: eth1_rxc_rx_clk
'#clock-cells':
description: |
@@ -74,6 +85,25 @@ required:
- '#power-domain-cells'
- '#reset-cells'
allOf:
- if:
properties:
compatible:
contains:
const: renesas,r9a08g046-cpg
then:
properties:
clocks:
minItems: 5
clock-names:
minItems: 5
else:
properties:
clocks:
maxItems: 1
clock-names:
maxItems: 1
additionalProperties: false
examples:
Bindings/clock/rockchip,rv1126b-cru.yaml
+1
View File
@@ -17,6 +17,7 @@ description:
properties:
compatible:
enum:
- rockchip,rv1103b-cru
- rockchip,rv1126b-cru
reg:
Bindings/clock/samsung,exynosautov920-clock.yaml
+21
View File
@@ -35,6 +35,7 @@ properties:
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-cpucl1
- samsung,exynosautov920-cmu-cpucl2
- samsung,exynosautov920-cmu-g3d
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
- samsung,exynosautov920-cmu-hsi2
@@ -287,6 +288,26 @@ allOf:
- const: oscclk
- const: noc
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-g3d
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_G3D SWITCH clock (from CMU_TOP)
- description: CMU_G3D NOCP clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: switch
- const: nocp
required:
- compatible
- "#clock-cells"
Bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
+54
View File
@@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module
maintainers:
- Anirudh Srinivasan <[email protected]>
description:
Multifunctional register block found in Tenstorrent Atlantis SoC whose main
function is to control clocks and resets. This block is instantiated multiple
times in the SoC, each block controls clock and resets for a different
subsystem. RCPU prcm serves low speed IO interfaces.
properties:
compatible:
enum:
- tenstorrent,atlantis-prcm-rcpu
reg:
maxItems: 1
clocks:
maxItems: 1
"#clock-cells":
const: 1
description:
See <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h> for valid indices.
"#reset-cells":
const: 1
required:
- compatible
- reg
- clocks
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@a8000000 {
compatible = "tenstorrent,atlantis-prcm-rcpu";
reg = <0xa8000000 0x10000>;
clocks = <&osc_24m>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Bindings/connector/pcie-m2-e-connector.yaml
+184
View File
@@ -0,0 +1,184 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PCIe M.2 Mechanical Key E Connector
maintainers:
- Manivannan Sadhasivam <[email protected]>
description:
A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E
connector. Mechanical Key E connectors are used to connect Wireless
Connectivity devices including combinations of Wi-Fi, BT, NFC to the host
machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.
properties:
compatible:
const: pcie-m2-e-connector
vpcie3v3-supply:
description: A phandle to the regulator for 3.3v supply.
vpcie1v8-supply:
description: A phandle to the regulator for VIO 1.8v supply.
i2c-parent:
$ref: /schemas/types.yaml#/definitions/phandle
description: I2C interface
clocks:
description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to
the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for
more details.
maxItems: 1
w-disable1-gpios:
description: GPIO output to W_DISABLE1# signal. This signal is used by the
host system to disable WiFi radio in the M.2 card. Refer, PCI Express M.2
Specification r4.0, sec 3.1.12.3 for more details.
maxItems: 1
w-disable2-gpios:
description: GPIO output to W_DISABLE2# signal. This signal is used by the
host system to disable BT radio in the M.2 card. Refer, PCI Express M.2
Specification r4.0, sec 3.1.12.3 for more details.
maxItems: 1
viocfg-gpios:
description: GPIO input to IO voltage configuration (VIO_CFG) signal. The
card drives this signal to indicate to the host system whether the card
supports an independent IO voltage domain for sideband signals. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.
maxItems: 1
uart-wake-gpios:
description: GPIO input to UART_WAKE# signal. The card asserts this signal
to wake the host system and initiate UART interface communication. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.8.1 for more details.
maxItems: 1
sdio-wake-gpios:
description: GPIO input to SDIO_WAKE# signal. The card asserts this signal
to wake the host system and initiate SDIO interface communication. Refer,
PCI Express M.2 Specification r4.0, sec 3.1.7 for more details.
maxItems: 1
sdio-reset-gpios:
description: GPIO output to SDIO_RESET# signal. This signal is used by the
host system to reset SDIO interface of the M.2 card. Refer, PCI Express
M.2 Specification r4.0, sec 3.1.7 for more details.
maxItems: 1
vendor-porta-gpios:
description: GPIO for the first vendor specific signal (VENDOR_PORTA). This
signal's functionality is defined by the card manufacturer and may be
used for proprietary features. Refer the card vendor's documentation for
details.
maxItems: 1
vendor-portb-gpios:
description: GPIO for the second vendor specific signal (VENDOR_PORTB). This
signal's functionality is defined by the card manufacturer and may be
used for proprietary features. Refer the card vendor's documentation for
details.
maxItems: 1
vendor-portc-gpios:
description: GPIO for the third vendor specific signal (VENDOR_PORTC). This
signal's functionality is defined by the card manufacturer and may be
used for proprietary features. Refer the card vendor's documentation for
details.
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
description: OF graph bindings modeling the interfaces exposed on the
connector. Since a single connector can have multiple interfaces, every
interface has an assigned OF graph port number as described below.
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: PCIe interface for Wi-Fi
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: SDIO interface for Wi-Fi
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: USB 2.0 interface for BT
port@3:
$ref: /schemas/graph.yaml#/properties/port
description: UART interface for BT
port@4:
$ref: /schemas/graph.yaml#/properties/port
description: PCM/I2S interface
anyOf:
- anyOf:
- required:
- port@0
- required:
- port@1
- anyOf:
- required:
- port@2
- required:
- port@3
required:
- compatible
- vpcie3v3-supply
additionalProperties: false
examples:
# PCI M.2 Key E connector for Wi-Fi/BT with PCIe/UART interfaces
- |
#include <dt-bindings/gpio/gpio.h>
connector {
compatible = "pcie-m2-e-connector";
vpcie3v3-supply = <&vreg_wcn_3p3>;
vpcie1v8-supply = <&vreg_l15b_1p8>;
i2c-parent = <&i2c0>;
w-disable1-gpios = <&tlmm 115 GPIO_ACTIVE_LOW>;
w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;
viocfg-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;
uart-wake-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;
sdio-wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;
sdio-reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <0>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&pcie4_port0_ep>;
};
};
port@3 {
reg = <3>;
#address-cells = <1>;
#size-cells = <0>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&uart14_ep>;
};
};
};
};
Bindings/connector/usb-connector.yaml
+37 -2
View File
@@ -300,6 +300,40 @@ properties:
$ref: /schemas/types.yaml#/definitions/uint8-array
maxItems: 4
sink-load-step:
description: Indicates the preferred load step slew rate in mA/usec for
the port (in sink mode). This property is defined in "6.5.13.7" of
"USB Power Delivery Specification Revision 3.1 Version 1.8".
$ref: /schemas/types.yaml#/definitions/uint32
enum: [150, 500]
default: 150
sink-load-characteristics:
description: Indicates the port's (in sink mode) preferred load
characteristics. Users can leverage SINK_LOAD_CHAR() defined in
dt-bindings/usb/pd.h to populate this field. This property is defined in
"6.5.13.8" of "USB Power Delivery Specification Revision 3.1 Version 1.8".
$ref: /schemas/types.yaml#/definitions/uint16
sink-compliance:
description: Represents the types of sources the sink device has been tested
and certified with. This property is defined in "6.5.13.9" of
"USB Power Delivery Specification Revision 3.1 Version 1.8"
Bit 0 when set indicates it has been tested on LPS compliant source
Bit 1 when set indicates it has been tested on PS1 compliant source
Bit 2 when set indicates it has been tested on PS2 compliant source
$ref: /schemas/types.yaml#/definitions/uint8
maximum: 7
charging-adapter-pdp-milliwatt:
description: This corresponds to the Power Delivery Profile rating of the
charging adapter shipped or recommended for use with the connector port.
This property is a requirement to infer the USB PD property
"SPR Sink Operational PDP" given in "6.5.13.14" of
"USB Power Delivery Specification Revision 3.1 Version 1.8".
minimum: 0
maximum: 100000
dependencies:
pd-disable: [typec-power-opmode]
sink-vdos-v1: [ sink-vdos ]
@@ -331,8 +365,9 @@ $defs:
"Universal Serial Bus Power Delivery Specification" chapter 6.4.1.3
Sink Capabilities Message, the order of each entry(PDO) should follow the
PD spec chapter 6.4.1. Required for power sink and power dual role. User
can specify the sink PDO array via PDO_FIXED/BATT/VAR/PPS_APDO() defined
in dt-bindings/usb/pd.h.
can specify the sink PDO array via
PDO_FIXED/BATT/VAR/PPS_APDO/SPR_AVS_SNK_APDO() defined in
dt-bindings/usb/pd.h.
minItems: 1
maxItems: 7
$ref: /schemas/types.yaml#/definitions/uint32-array
Bindings/cpufreq/cpufreq-qcom-hw.yaml
+1
View File
@@ -35,6 +35,7 @@ properties:
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
- qcom,eliza-cpufreq-epss
- qcom,milos-cpufreq-epss
- qcom,qcs8300-cpufreq-epss
- qcom,qdu1000-cpufreq-epss
Bindings/crypto/inside-secure,safexcel.yaml
+4 -1
View File
@@ -18,6 +18,7 @@ properties:
- items:
- enum:
- marvell,armada-3700-crypto
- mediatek,mt7981-crypto
- mediatek,mt7986-crypto
- const: inside-secure,safexcel-eip97ies
- const: inside-secure,safexcel-eip197b
@@ -80,7 +81,9 @@ allOf:
compatible:
not:
contains:
const: mediatek,mt7986-crypto
enum:
- mediatek,mt7981-crypto
- mediatek,mt7986-crypto
then:
properties:
interrupts:
Bindings/crypto/qcom,inline-crypto-engine.yaml
+61 -1
View File
@@ -13,6 +13,7 @@ properties:
compatible:
items:
- enum:
- qcom,eliza-inline-crypto-engine
- qcom,kaanapali-inline-crypto-engine
- qcom,milos-inline-crypto-engine
- qcom,qcs8300-inline-crypto-engine
@@ -29,8 +30,23 @@ properties:
maxItems: 1
clocks:
minItems: 1
maxItems: 2
clock-names:
minItems: 1
items:
- const: core
- const: iface
power-domains:
maxItems: 1
operating-points-v2: true
opp-table:
type: object
required:
- compatible
- reg
@@ -38,6 +54,25 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- qcom,eliza-inline-crypto-engine
- qcom,milos-inline-crypto-engine
then:
required:
- power-domains
- clock-names
properties:
clocks:
minItems: 2
clock-names:
minItems: 2
examples:
- |
#include <dt-bindings/clock/qcom,sm8550-gcc.h>
@@ -46,6 +81,31 @@ examples:
compatible = "qcom,sm8550-inline-crypto-engine",
"qcom,inline-crypto-engine";
reg = <0x01d88000 0x8000>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>;
clock-names = "core",
"iface";
power-domains = <&gcc UFS_PHY_GDSC>;
operating-points-v2 = <&ice_opp_table>;
ice_opp_table: opp-table {
compatible = "operating-points-v2";
opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-201500000 {
opp-hz = /bits/ 64 <201500000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-403000000 {
opp-hz = /bits/ 64 <403000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
};
...
Bindings/display/apple,h7-display-pipe-mipi.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple pre-DCP display controller MIPI interface
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
- Sasha Finkelstein <k@chaosmail.tech>
description:
The MIPI controller part of the pre-DCP Apple display controller
Bindings/display/apple,h7-display-pipe.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple pre-DCP display controller
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
- Sasha Finkelstein <k@chaosmail.tech>
description:
A secondary display controller used to drive the "touchbar" on
Bindings/display/arm,komeda.yaml
+3 -1
View File
@@ -19,7 +19,9 @@ properties:
compatible:
oneOf:
- items:
- const: arm,mali-d32
- enum:
- arm,mali-d32
- armchina,linlon-d6
- const: arm,mali-d71
- const: arm,mali-d71
Bindings/display/bridge/analogix,anx7625.yaml
+97 -1
View File
@@ -85,6 +85,11 @@ properties:
aux-bus:
$ref: /schemas/display/dp-aux-bus.yaml#
connector:
type: object
$ref: /schemas/connector/usb-connector.yaml#
unevaluatedProperties: false
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -117,7 +122,6 @@ properties:
required:
- port@0
- port@1
required:
- compatible
@@ -127,6 +131,28 @@ required:
- vdd33-supply
- ports
allOf:
- if:
required:
- aux-bus
- connector
then:
false
- if:
required:
- connector
then:
properties:
ports:
properties:
port@1: false
else:
properties:
ports:
required:
- port@1
additionalProperties: false
examples:
@@ -185,3 +211,73 @@ examples:
};
};
};
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
encoder@58 {
compatible = "analogix,anx7625";
reg = <0x58>;
enable-gpios = <&pio 45 GPIO_ACTIVE_HIGH>;
reset-gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
vdd10-supply = <&pp1000_mipibrdg>;
vdd18-supply = <&pp1800_mipibrdg>;
vdd33-supply = <&pp3300_mipibrdg>;
analogix,audio-enable;
analogix,lane0-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
analogix,lane1-swing = /bits/ 8 <0x14 0x54 0x64 0x74>;
connector {
compatible = "usb-c-connector";
power-role = "dual";
data-role = "dual";
vbus-supply = <&vbus_reg>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&usb_hs>;
};
};
port@1 {
reg = <1>;
endpoint {
remote-endpoint = <&usb_ss>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&usb_sbu>;
};
};
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
endpoint {
remote-endpoint = <&mipi_dsi>;
bus-type = <7>;
data-lanes = <0 1 2 3>;
};
};
};
};
};
Bindings/display/bridge/fsl,ldb.yaml
+18
View File
@@ -35,6 +35,15 @@ properties:
- const: ldb
- const: lvds
nxp,enable-termination-resistor:
type: boolean
description:
Indicates that the built-in 100 Ohm termination resistor on the LVDS
output is enabled. This property is optional and controlled via the
HS_EN bit in the LVDS_CTRL register. Enabling it can improve signal
quality and prevent visual artifacts on some boards, but increases
power consumption.
ports:
$ref: /schemas/graph.yaml#/properties/ports
@@ -84,6 +93,15 @@ allOf:
required:
- reg-names
- if:
properties:
compatible:
contains:
const: fsl,imx6sx-ldb
then:
properties:
nxp,enable-termination-resistor: false
additionalProperties: false
examples:
Bindings/display/bridge/lontium,lt8713sx.yaml
+113
View File
@@ -0,0 +1,113 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/lontium,lt8713sx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Lontium LT8713SX Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0/DP++ bridge-hub
maintainers:
- Vishnu Saini <[email protected]>
description:
The Lontium LT8713SX is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter
that integrates one DP input and up to three configurable output interfaces
(DP1.4 / HDMI2.0 / DP++), with SST/MST functionality and audio support.
properties:
compatible:
enum:
- lontium,lt8713sx
reg:
maxItems: 1
vcc-supply:
description: Regulator for 3.3V vcc.
vdd-supply:
description: Regulator for 1.1V vdd.
reset-gpios:
description: GPIO connected to active low RESET pin.
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
DP port for DP input from soc to bridge chip
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
DP port for DP output from bridge
port@2:
$ref: /schemas/graph.yaml#/properties/port
description:
Additional DP port for DP output from bridge
port@3:
$ref: /schemas/graph.yaml#/properties/port
description:
Additional DP port for DP output from bridge
required:
- port@0
required:
- compatible
- reg
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@4f {
compatible = "lontium,lt8713sx";
reg = <0x4f>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
lt8713sx_dp_in: endpoint {
remote-endpoint = <&mdss_dp0_out>;
};
};
port@1 {
reg = <1>;
lt8713sx_dp0_out: endpoint {
remote-endpoint = <&dp0_connector_in>;
};
};
port@2 {
reg = <2>;
lt8713sx_dp1_out: endpoint {
remote-endpoint = <&dp1_connector_in>;
};
};
port@3 {
reg = <3>;
lt8713sx_dp2_out: endpoint {
remote-endpoint = <&dp2_connector_in>;
};
};
};
};
};
Bindings/display/bridge/lontium,lt8912b.yaml
-3
View File
@@ -39,9 +39,6 @@ properties:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes: true
required:
- data-lanes
Bindings/display/bridge/lontium,lt9611.yaml
+11 -4
View File
@@ -44,21 +44,28 @@ properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description:
Primary MIPI port-1 for MIPI input
DSI Port A input. directly drives the display, or works in
combination with Port B for higher resolution displays.
port@1:
$ref: /schemas/graph.yaml#/properties/port
description:
Additional MIPI port-2 for MIPI input, used in combination
with primary MIPI port-1 to drive higher resolution displays
DSI Port B input. Can be used alone if DSI is physically
connected to Port B, or in combination with Port A for higher
resolution displays.
port@2:
$ref: /schemas/graph.yaml#/properties/port
description:
HDMI port for HDMI output
anyOf:
- required:
- port@0
- required:
- port@1
required:
- port@0
- port@2
required:
Bindings/display/bridge/lvds-codec.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
oneOf:
- items:
- enum:
- doestek,dtc34lm85am # For the Doestek DTC34LM85AM Flat Panel Display (FPD) Transmitter
- onnn,fin3385 # OnSemi FIN3385
- ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer
- ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer
Bindings/display/bridge/thead,th1520-dw-hdmi.yaml
+120
View File
@@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/bridge/thead,th1520-dw-hdmi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: T-Head TH1520 DesignWare HDMI TX Encoder
maintainers:
- Icenowy Zheng <[email protected]>
description:
The HDMI transmitter is a Synopsys DesignWare HDMI TX controller
paired with a DesignWare HDMI Gen2 TX PHY.
allOf:
- $ref: /schemas/display/bridge/synopsys,dw-hdmi.yaml#
properties:
compatible:
enum:
- thead,th1520-dw-hdmi
reg-io-width:
const: 4
clocks:
maxItems: 4
clock-names:
items:
- const: iahb
- const: isfr
- const: cec
- const: pix
resets:
items:
- description: Main reset
- description: Configuration APB reset
reset-names:
items:
- const: main
- const: apb
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/properties/port
description: Input port connected to DC8200 DPU "DP" output
port@1:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI output port
required:
- port@0
- port@1
required:
- compatible
- reg
- reg-io-width
- clocks
- clock-names
- resets
- reset-names
- interrupts
- ports
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/clock/thead,th1520-clk-ap.h>
#include <dt-bindings/reset/thead,th1520-reset.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
hdmi@ffef540000 {
compatible = "thead,th1520-dw-hdmi";
reg = <0xff 0xef540000 0x0 0x40000>;
reg-io-width = <4>;
interrupts = <111 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clk_vo CLK_HDMI_PCLK>,
<&clk_vo CLK_HDMI_SFR>,
<&clk_vo CLK_HDMI_CEC>,
<&clk_vo CLK_HDMI_PIXCLK>;
clock-names = "iahb", "isfr", "cec", "pix";
resets = <&rst_vo TH1520_RESET_ID_HDMI>,
<&rst_vo TH1520_RESET_ID_HDMI_APB>;
reset-names = "main", "apb";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
hdmi_in: endpoint {
remote-endpoint = <&dpu_out_dp1>;
};
};
port@1 {
reg = <1>;
hdmi_out_conn: endpoint {
remote-endpoint = <&hdmi_conn_in>;
};
};
};
};
};
Bindings/display/bridge/waveshare,dsi2dpi.yaml
+3
View File
@@ -40,9 +40,12 @@ properties:
properties:
data-lanes:
description: array of physical DSI data lane indexes.
minItems: 1
items:
- const: 1
- const: 2
- const: 3
- const: 4
required:
- data-lanes
Bindings/display/mediatek/mediatek,aal.yaml
+1
View File
@@ -33,6 +33,7 @@ properties:
- enum:
- mediatek,mt2712-disp-aal
- mediatek,mt6795-disp-aal
- mediatek,mt8167-disp-aal
- const: mediatek,mt8173-disp-aal
- items:
- enum:
Bindings/display/mediatek/mediatek,ccorr.yaml
+3 -1
View File
@@ -25,7 +25,9 @@ properties:
- mediatek,mt8183-disp-ccorr
- mediatek,mt8192-disp-ccorr
- items:
- const: mediatek,mt8365-disp-ccorr
- enum:
- mediatek,mt8167-disp-ccorr
- mediatek,mt8365-disp-ccorr
- const: mediatek,mt8183-disp-ccorr
- items:
- enum:
Bindings/display/mediatek/mediatek,dither.yaml
+1
View File
@@ -26,6 +26,7 @@ properties:
- mediatek,mt8183-disp-dither
- items:
- enum:
- mediatek,mt8167-disp-dither
- mediatek,mt8186-disp-dither
- mediatek,mt8188-disp-dither
- mediatek,mt8192-disp-dither
Bindings/display/mediatek/mediatek,gamma.yaml
+1
View File
@@ -28,6 +28,7 @@ properties:
- items:
- enum:
- mediatek,mt6795-disp-gamma
- mediatek,mt8167-disp-gamma
- const: mediatek,mt8173-disp-gamma
- items:
- enum:
Bindings/display/mediatek/mediatek,ovl.yaml
+1
View File
@@ -23,6 +23,7 @@ properties:
oneOf:
- enum:
- mediatek,mt2701-disp-ovl
- mediatek,mt8167-disp-ovl
- mediatek,mt8173-disp-ovl
- mediatek,mt8183-disp-ovl
- mediatek,mt8192-disp-ovl
Bindings/display/mediatek/mediatek,rdma.yaml
+1
View File
@@ -36,6 +36,7 @@ properties:
- enum:
- mediatek,mt7623-disp-rdma
- mediatek,mt2712-disp-rdma
- mediatek,mt8167-disp-rdma
- const: mediatek,mt2701-disp-rdma
- items:
- enum:
Bindings/display/mediatek/mediatek,wdma.yaml
+3 -1
View File
@@ -24,7 +24,9 @@ properties:
- enum:
- mediatek,mt8173-disp-wdma
- items:
- const: mediatek,mt6795-disp-wdma
- enum:
- mediatek,mt6795-disp-wdma
- mediatek,mt8167-disp-wdma
- const: mediatek,mt8173-disp-wdma
reg:
Bindings/display/msm/dp-controller.yaml
+24 -5
View File
@@ -67,6 +67,7 @@ properties:
- items:
- enum:
- qcom,eliza-dp
- qcom,sm8750-dp
- const: qcom,sm8650-dp
@@ -218,6 +219,7 @@ allOf:
- required:
- "#sound-dai-cells"
else:
$ref: /schemas/sound/dai-common.yaml#
properties:
aux-bus: false
required:
@@ -242,7 +244,7 @@ allOf:
clocks:
minItems: 5
maxItems: 5
clocks-names:
clock-names:
minItems: 5
maxItems: 5
@@ -263,7 +265,7 @@ allOf:
clocks:
minItems: 5
maxItems: 6
clocks-names:
clock-names:
minItems: 5
maxItems: 6
@@ -276,7 +278,6 @@ allOf:
- qcom,sc8180x-dp
- qcom,sdm845-dp
- qcom,sm8350-dp
- qcom,sm8650-dp
then:
properties:
reg:
@@ -285,6 +286,24 @@ allOf:
clocks:
minItems: 6
maxItems: 6
clock-names:
minItems: 6
maxItems: 6
- if:
properties:
compatible:
contains:
enum:
- qcom,sm8650-dp
then:
properties:
reg:
minItems: 5
maxItems: 9
clocks:
minItems: 6
maxItems: 6
clocks-names:
minItems: 6
maxItems: 6
@@ -305,7 +324,7 @@ allOf:
clocks:
minItems: 6
maxItems: 8
clocks-names:
clock-names:
minItems: 6
maxItems: 8
@@ -325,7 +344,7 @@ allOf:
clocks:
minItems: 5
maxItems: 6
clocks-names:
clock-names:
minItems: 5
maxItems: 6
Bindings/display/msm/dsi-controller-main.yaml
+5
View File
@@ -49,8 +49,13 @@ properties:
- items:
- enum:
- qcom,qcs8300-dsi-ctrl
- qcom,sc8280xp-dsi-ctrl
- const: qcom,sa8775p-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- items:
- const: qcom,eliza-dsi-ctrl
- const: qcom,sm8750-dsi-ctrl
- const: qcom,mdss-dsi-ctrl
- enum:
- qcom,dsi-ctrl-6g-qcm2290
- qcom,mdss-dsi-ctrl # This should always come with an SoC-specific compatible
Bindings/display/msm/gmu.yaml
+1
View File
@@ -91,6 +91,7 @@ allOf:
compatible:
contains:
enum:
- qcom,adreno-gmu-615.0
- qcom,adreno-gmu-618.0
- qcom,adreno-gmu-630.2
then:
Bindings/display/msm/gpu.yaml
-7
View File
@@ -440,13 +440,6 @@ allOf:
clocks: false
clock-names: false
reg-names:
minItems: 1
items:
- const: kgsl_3d0_reg_memory
- const: cx_mem
- const: cx_dbgc
examples:
- |
Bindings/display/msm/qcom,eliza-mdss.yaml
+498
View File
@@ -0,0 +1,498 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/msm/qcom,eliza-mdss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Eliza SoC Display MDSS
maintainers:
- Krzysztof Kozlowski <[email protected]>
description:
Eliza SoC Mobile Display Subsystem (MDSS) encapsulates sub-blocks like DPU
display controller, DSI and DP interfaces etc.
$ref: /schemas/display/msm/mdss-common.yaml#
properties:
compatible:
const: qcom,eliza-mdss
clocks:
items:
- description: Display AHB
- description: Display hf AXI
- description: Display core
iommus:
maxItems: 1
interconnects:
items:
- description: Interconnect path from mdp0 port to the data bus
- description: Interconnect path from CPU to the reg bus
interconnect-names:
items:
- const: mdp0-mem
- const: cpu-cfg
patternProperties:
"^display-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,eliza-dpu
"^displayport-controller@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,eliza-dp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,eliza-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,eliza-dsi-phy-4nm
required:
- compatible
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
display-subsystem@ae00000 {
compatible = "qcom,eliza-mdss";
reg = <0x0ae00000 0x1000>;
reg-names = "mdss";
ranges;
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&disp_cc_mdss_ahb_clk>,
<&gcc_disp_hf_axi_clk>,
<&disp_cc_mdss_mdp_clk>;
resets = <&disp_cc_mdss_core_bcr>;
interconnects = <&mmss_noc_master_mdp QCOM_ICC_TAG_ALWAYS
&mc_virt_slave_ebi1 QCOM_ICC_TAG_ALWAYS>,
<&gem_noc_master_appss_proc QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc_slave_display_cfg QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "mdp0-mem",
"cpu-cfg";
power-domains = <&mdss_gdsc>;
iommus = <&apps_smmu 0x800 0x2>;
interrupt-controller;
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <1>;
mdss_mdp: display-controller@ae01000 {
compatible = "qcom,eliza-dpu";
reg = <0x0ae01000 0x93000>,
<0x0aeb0000 0x3000>;
reg-names = "mdp",
"vbif";
interrupts-extended = <&mdss 0>;
clocks = <&gcc_disp_hf_axi_clk>,
<&disp_cc_mdss_ahb_clk>,
<&disp_cc_mdss_mdp_lut_clk>,
<&disp_cc_mdss_mdp_clk>,
<&disp_cc_mdss_vsync_clk>;
clock-names = "nrt_bus",
"iface",
"lut",
"core",
"vsync";
assigned-clocks = <&disp_cc_mdss_vsync_clk>;
assigned-clock-rates = <19200000>;
operating-points-v2 = <&mdp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss_dsi0_in>;
};
};
port@1 {
reg = <1>;
dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
port@2 {
reg = <2>;
dpu_intf0_out: endpoint {
remote-endpoint = <&mdss_dp0_in>;
};
};
};
mdp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-150000000 {
opp-hz = /bits/ 64 <150000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};
opp-207000000 {
opp-hz = /bits/ 64 <207000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-417000000 {
opp-hz = /bits/ 64 <417000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-532000000 {
opp-hz = /bits/ 64 <532000000>;
required-opps = <&rpmhpd_opp_nom>;
};
opp-600000000 {
opp-hz = /bits/ 64 <600000000>;
required-opps = <&rpmhpd_opp_nom_l1>;
};
opp-660000000 {
opp-hz = /bits/ 64 <660000000>;
required-opps = <&rpmhpd_opp_turbo>;
};
};
};
dsi@ae94000 {
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0ae94000 0x400>;
reg-names = "dsi_ctrl";
interrupts-extended = <&mdss 4>;
clocks = <&disp_cc_mdss_byte0_clk>,
<&disp_cc_mdss_byte0_intf_clk>,
<&disp_cc_mdss_pclk0_clk>,
<&disp_cc_mdss_esc0_clk>,
<&disp_cc_mdss_ahb_clk>,
<&gcc_disp_hf_axi_clk>,
<&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>,
<&mdss_dsi0_phy DSI_BYTE_PLL_CLK>,
<&disp_cc_esync0_clk>,
<&disp_cc_osc_clk>,
<&disp_cc_mdss_byte0_clk_src>,
<&disp_cc_mdss_pclk0_clk_src>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus",
"dsi_pll_pixel",
"dsi_pll_byte",
"esync",
"osc",
"byte_src",
"pixel_src";
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi0_phy>;
phy-names = "dsi";
#address-cells = <1>;
#size-cells = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi0_out: endpoint {
remote-endpoint = <&panel0_in>;
data-lanes = <0 1 2 3>;
};
};
};
mdss_dsi_opp_table: opp-table {
compatible = "operating-points-v2";
opp-140630000 {
opp-hz = /bits/ 64 <140630000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};
opp-187500000 {
opp-hz = /bits/ 64 <187500000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-300000000 {
opp-hz = /bits/ 64 <300000000>;
required-opps = <&rpmhpd_opp_svs>;
};
opp-358000000 {
opp-hz = /bits/ 64 <358000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
};
};
mdss_dsi0_phy: phy@ae95000 {
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
reg = <0x0ae95000 0x200>,
<0x0ae95200 0x300>,
<0x0ae95500 0x400>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&disp_cc_mdss_ahb_clk>,
<&bi_tcxo_div2>;
clock-names = "iface",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;
vdds-supply = <&vreg_l2b>;
};
dsi@ae96000 {
compatible = "qcom,eliza-dsi-ctrl", "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0x0ae96000 0x400>;
reg-names = "dsi_ctrl";
interrupts-extended = <&mdss 5>;
clocks = <&disp_cc_mdss_byte1_clk>,
<&disp_cc_mdss_byte1_intf_clk>,
<&disp_cc_mdss_pclk1_clk>,
<&disp_cc_mdss_esc1_clk>,
<&disp_cc_mdss_ahb_clk>,
<&gcc_disp_hf_axi_clk>,
<&mdss_dsi1_phy DSI_PIXEL_PLL_CLK>,
<&mdss_dsi1_phy DSI_BYTE_PLL_CLK>,
<&disp_cc_esync1_clk>,
<&disp_cc_osc_clk>,
<&disp_cc_mdss_byte1_clk_src>,
<&disp_cc_mdss_pclk1_clk_src>;
clock-names = "byte",
"byte_intf",
"pixel",
"core",
"iface",
"bus",
"dsi_pll_pixel",
"dsi_pll_byte",
"esync",
"osc",
"byte_src",
"pixel_src";
operating-points-v2 = <&mdss_dsi_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&mdss_dsi1_phy>;
phy-names = "dsi";
vdda-supply = <&vreg_l4b>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dsi1_in: endpoint {
remote-endpoint = <&dpu_intf2_out>;
};
};
port@1 {
reg = <1>;
mdss_dsi1_out: endpoint {
remote-endpoint = <&panel1_in>;
data-lanes = <0 1 2 3>;
};
};
};
};
mdss_dsi1_phy: phy@ae97000 {
compatible = "qcom,eliza-dsi-phy-4nm", "qcom,sm8650-dsi-phy-4nm";
reg = <0x0ae97000 0x200>,
<0x0ae97200 0x300>,
<0x0ae97500 0x400>;
reg-names = "dsi_phy",
"dsi_phy_lane",
"dsi_pll";
clocks = <&disp_cc_mdss_ahb_clk>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface",
"ref";
#clock-cells = <1>;
#phy-cells = <0>;
vdds-supply = <&vreg_l2b>;
};
displayport-controller@af54000 {
compatible = "qcom,eliza-dp", "qcom,sm8650-dp";
reg = <0x0af54000 0x200>,
<0x0af54200 0x200>,
<0x0af55000 0xc00>,
<0x0af56000 0x400>,
<0x0af57000 0x400>,
<0x0af58000 0x400>,
<0x0af59000 0x400>,
<0x0af5a000 0x600>,
<0x0af5b000 0x600>;
interrupts-extended = <&mdss 12>;
clocks = <&disp_cc_mdss_ahb_clk>,
<&disp_cc_mdss_dptx0_aux_clk>,
<&disp_cc_mdss_dptx0_link_clk>,
<&disp_cc_mdss_dptx0_link_intf_clk>,
<&disp_cc_mdss_dptx0_pixel0_clk>,
<&disp_cc_mdss_dptx0_pixel1_clk>;
clock-names = "core_iface",
"core_aux",
"ctrl_link",
"ctrl_link_iface",
"stream_pixel",
"stream_1_pixel";
assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>,
<&disp_cc_mdss_dptx0_pixel0_clk_src>,
<&disp_cc_mdss_dptx0_pixel1_clk_src>;
assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
operating-points-v2 = <&dp_opp_table>;
power-domains = <&rpmhpd RPMHPD_MMCX>;
phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>;
phy-names = "dp";
#sound-dai-cells = <0>;
dp_opp_table: opp-table {
compatible = "operating-points-v2";
opp-192000000 {
opp-hz = /bits/ 64 <192000000>;
required-opps = <&rpmhpd_opp_low_svs_d1>;
};
opp-270000000 {
opp-hz = /bits/ 64 <270000000>;
required-opps = <&rpmhpd_opp_low_svs>;
};
opp-540000000 {
opp-hz = /bits/ 64 <540000000>;
required-opps = <&rpmhpd_opp_svs_l1>;
};
opp-810000000 {
opp-hz = /bits/ 64 <810000000>;
required-opps = <&rpmhpd_opp_nom>;
};
};
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mdss_dp0_in: endpoint {
remote-endpoint = <&dpu_intf0_out>;
};
};
port@1 {
reg = <1>;
mdss_dp0_out: endpoint {
data-lanes = <0 1 2 3>;
remote-endpoint = <&usb_dp_qmpphy_dp_in>;
link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000 8100000000>;
};
};
};
};
};
Bindings/display/msm/qcom,sc8280xp-mdss.yaml
+30
View File
@@ -50,6 +50,22 @@ patternProperties:
- qcom,sc8280xp-dp
- qcom,sc8280xp-edp
"^dsi@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,sc8280xp-dsi-ctrl
"^phy@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: qcom,sc8280xp-dsi-phy-5nm
unevaluatedProperties: false
examples:
@@ -129,6 +145,20 @@ examples:
};
};
port@1 {
reg = <1>;
dpu_intf1_out: endpoint {
remote-endpoint = <&mdss0_dsi0_in>;
};
};
port@2 {
reg = <2>;
dpu_intf2_out: endpoint {
remote-endpoint = <&mdss0_dsi1_in>;
};
};
port@4 {
reg = <4>;
endpoint {
Bindings/display/msm/qcom,sm8650-dpu.yaml
+2 -1
View File
@@ -15,6 +15,7 @@ properties:
compatible:
oneOf:
- enum:
- qcom,eliza-dpu
- qcom,glymur-dpu
- qcom,kaanapali-dpu
- qcom,sa8775p-dpu
@@ -69,7 +70,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8650-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
<0x0aeb0000 0x3000>;
reg-names = "mdp", "vbif";
clocks = <&gcc_axi_clk>,
Bindings/display/msm/qcom,sm8650-mdss.yaml
+1 -1
View File
@@ -112,7 +112,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8650-dpu";
reg = <0x0ae01000 0x8f000>,
<0x0aeb0000 0x2008>;
<0x0aeb0000 0x3000>;
reg-names = "mdp", "vbif";
clocks = <&gcc_axi_clk>,
Bindings/display/msm/qcom,sm8750-mdss.yaml
+10 -6
View File
@@ -117,7 +117,7 @@ examples:
display-controller@ae01000 {
compatible = "qcom,sm8750-dpu";
reg = <0x0ae01000 0x93000>,
<0x0aeb0000 0x2008>;
<0x0aeb0000 0x3000>;
reg-names = "mdp",
"vbif";
@@ -389,11 +389,15 @@ examples:
displayport-controller@af54000 {
compatible = "qcom,sm8750-dp", "qcom,sm8650-dp";
reg = <0xaf54000 0x104>,
<0xaf54200 0xc0>,
<0xaf55000 0x770>,
<0xaf56000 0x9c>,
<0xaf57000 0x9c>;
reg = <0x0af54000 0x200>,
<0x0af54200 0x200>,
<0x0af55000 0xc00>,
<0x0af56000 0x400>,
<0x0af57000 0x400>,
<0x0af58000 0x400>,
<0x0af59000 0x400>,
<0x0af5a000 0x600>,
<0x0af5b000 0x600>;
interrupts-extended = <&mdss 12>;
Bindings/display/panel/abt,y030xx067a.yaml
-5
View File
@@ -20,11 +20,6 @@ properties:
reg:
maxItems: 1
backlight: true
port: true
power-supply: true
reset-gpios: true
required:
- compatible
- reg
Bindings/display/panel/advantech,idk-1110wr.yaml
+2 -2
View File
@@ -41,8 +41,6 @@ properties:
panel-timing: true
port: true
additionalProperties: false
required:
- compatible
- data-mapping
@@ -51,6 +49,8 @@ required:
- panel-timing
- port
additionalProperties: false
examples:
- |+
panel {
Bindings/display/panel/advantech,idk-2121wr.yaml
+2 -2
View File
@@ -56,8 +56,6 @@ properties:
- port@0
- port@1
additionalProperties: false
required:
- compatible
- width-mm
@@ -65,6 +63,8 @@ required:
- data-mapping
- panel-timing
additionalProperties: false
examples:
- |+
panel-lvds {
Bindings/display/panel/apple,summit.yaml
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple "Summit" display panel
maintainers:
- Sasha Finkelstein <fnkl.kernel@gmail.com>
- Sasha Finkelstein <k@chaosmail.tech>
description:
An OLED panel used as a touchbar on certain Apple laptops.
Bindings/display/panel/bananapi,s070wv20-ct16.yaml
+2 -2
View File
@@ -22,10 +22,10 @@ properties:
enable-gpios: true
port: true
additionalProperties: false
required:
- compatible
- power-supply
additionalProperties: false
...
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