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MFC r308286,r308287:

Browse Source 
r308286:
    TEGRA: Add basic driver for memory controller.  For now, it only reports
    memory and SMMU access errors.
  r308287:
    TEGRA: Fix numerous issues in clock code.  Define and export clocks related
    to XUSB driver.
This commit is contained in:
Michal Meloun committed 2017-04-16 08:18:37 +00:00
1 parent 6f2e340f2f
commit e311d44bd6
5 files changed
+471 -124
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/stable/11/; revision=317012
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sys/arm/nvidia/tegra124/files.tegra124
+1
View File
@@ -33,6 +33,7 @@ arm/nvidia/tegra_efuse.c standard
arm/nvidia/tegra_soctherm_if.m standard
arm/nvidia/tegra_soctherm.c standard
arm/nvidia/tegra_lic.c standard
arm/nvidia/tegra_mc.c standard
#arm/nvidia/tegra_hda.c optional snd_hda
#arm/nvidia/drm2/hdmi.c optional drm2
#arm/nvidia/drm2/tegra_drm_if.m optional drm2
sys/arm/nvidia/tegra124/tegra124_car.c
+8 -4
View File
@@ -191,13 +191,13 @@ PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};
PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};
PLIST(mux_pllmcp_clkm) = {"pllM_out0", "pllC_out0", "pllP_out0", "clk_m",
"pllM_UD", "pllC2_out0", "pllC3_out0", "pllC_UD"};
PLIST(mux_xusb_hs) = {"pc_xusb_ss", "pllU_60"};
PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};
PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};
/* Clocks ajusted online. */
static struct clk_fixed_def fixed_clk_m =
FRATE(0, "clk_m", 12000000);
FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000);
static struct clk_fixed_def fixed_osc_div_clk =
FACT(0, "osc_div_clk", "clk_m", 1, 1);
@@ -222,6 +222,10 @@ static struct clk_fixed_def tegra124_fixed_clks[] = {
FRATE(0, "audio3", 10000000),
FRATE(0, "audio4", 10000000),
FRATE(0, "ext_vimclk", 10000000),
/* XUSB */
FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2),
};
@@ -239,7 +243,7 @@ static struct clk_mux_def tegra124_mux_clks[] = {
MUX(0, "emc_mux", mux_pllmcp_clkm, CLK_SOURCE_EMC, 29, 3),
/* USB. */
MUX(0, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
};
@@ -249,7 +253,7 @@ static struct clk_gate_def tegra124_gate_clks[] = {
/* Core clocks. */
GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0),
GATE_PLL(0, "pllU_480", "pllU_out", PLLU_BASE, 22),
GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0),
GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16),
sys/arm/nvidia/tegra124/tegra124_clk_per.c
+123 -110
View File
@@ -41,6 +41,15 @@ __FBSDID("$FreeBSD$");
#include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
#include "tegra124_car.h"
/* The TEGRA124_CLK_XUSB_GATE is missing in current
* DT bindings, define it localy
*/
#ifdef TEGRA124_CLK_XUSB_GATE
#error "TEGRA124_CLK_XUSB_GATE is now defined, revisit XUSB code!"
#else
#define TEGRA124_CLK_XUSB_GATE 143
#endif
/* Bits in base register. */
#define PERLCK_AMUX_MASK 0x0F
#define PERLCK_AMUX_SHIFT 16
@@ -175,7 +184,7 @@ PLIST(mux_sep_audio) =
"spdif_in", "i2s0", "i2s1", "i2s2",
"i2s4", "pllA_out0", "ext_vimclk"};
static uint32_t clk_enabale_reg[] = {
static uint32_t clk_enable_reg[] = {
CLK_OUT_ENB_L,
CLK_OUT_ENB_H,
CLK_OUT_ENB_U,
@@ -285,7 +294,7 @@ static struct pgate_def pgate_def[] = {
GATE(CSUS, "sus_out", "clk_m", U(28)),
/* GATE(DEVD2_OUT, "devd2_out", "clk_m", U(29)), */
/* GATE(DEVD1_OUT, "devd1_out", "clk_m", U(30)), */
GATE(XUSB_DEV_SRC, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
GATE(XUSB_DEV, "xusb_core_dev", "pc_xusb_core_dev", U(31)),
/* bank V -> 96-127 */
/* GATE(CPUG, "cpug", "clk_m", V(0)), */
@@ -328,7 +337,7 @@ static struct pgate_def pgate_def[] = {
/* GATE(HDMI_IOBIST, "hdmi_iobist", "clk_m", W(11)), */
/* GATE(SATA_IOBIST, "sata_iobist", "clk_m", W(12)), */
/* GATE(MIPI_IOBIST, "mipi_iobist", "clk_m", W(13)), */
/* GATE(XUSB_IOBIST, "xusb_iobist", "clk_m", W(15)), */
GATE(XUSB_GATE, "xusb_gate", "clk_m", W(15)),
GATE(CILAB, "cilab", "pc_cilab", W(16)),
GATE(CILCD, "cilcd", "pc_cilcd", W(17)),
GATE(CILE, "cile", "pc_cile", W(18)),
@@ -337,10 +346,10 @@ static struct pgate_def pgate_def[] = {
GATE(ENTROPY, "entropy", "pc_entropy", W(21)),
GATE(AMX, "amx", "pc_amx", W(25)),
GATE(ADX, "adx", "pc_adx", W(26)),
GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", X(27)),
GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", X(27)),
GATE(XUSB_SS_SRC, "xusb_ss", "xusb_ss_mux", X(28)),
/* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", X(29)), */
GATE(DFLL_REF, "dvfs_ref", "pc_dvfs_ref", W(27)),
GATE(DFLL_SOC, "dvfs_soc", "pc_dvfs_soc", W(27)),
GATE(XUSB_SS, "xusb_ss", "xusb_ss_mux", W(28)),
/* GATE(EMC_LATENCY, "emc_latency", "pc_emc_latency", W(29)), */
/* bank X -> 160-191*/
/* GATE(SPARE, "spare", "clk_m", X(0)), */
@@ -391,111 +400,115 @@ static struct pgate_def pgate_def[] = {
}
/* Mux with fractional 8.1 divider. */
#define CLK_8_1(cn, pl, r, f) \
PER_CLK(0, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
#define CLK_8_1(id, cn, pl, r, f) \
PER_CLK(id, cn, pl, r, 8, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
/* Mux with fractional 16.1 divider. */
#define CLK16_1(cn, pl, r, f) \
PER_CLK(0, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
#define CLK16_1(id, cn, pl, r, f) \
PER_CLK(id, cn, pl, r, 16, 1, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
/* Mux with integer 16bits divider. */
#define CLK16_0(cn, pl, r, f) \
PER_CLK(0, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
#define CLK16_0(id, cn, pl, r, f) \
PER_CLK(id, cn, pl, r, 16, 0, (f) | DCF_HAVE_MUX | DCF_HAVE_DIV)
/* Mux wihout divider. */
#define CLK_0_0(cn, pl, r, f) \
PER_CLK(0, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX)
#define CLK_0_0(id, cn, pl, r, f) \
PER_CLK(id, cn, pl, r, 0, 0, (f) | DCF_HAVE_MUX)
static struct periph_def periph_def[] = {
CLK_8_1("pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),
CLK_8_1("pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
CLK_8_1("pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
CLK_8_1("pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0),
CLK_8_1("pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0),
CLK_8_1("pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0),
CLK_8_1("pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0),
CLK16_0("pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0),
CLK16_0("pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0),
CLK_8_1("pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0),
CLK_0_0("pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0),
CLK_0_0("pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0),
CLK_8_1("pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
CLK_8_1("pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI),
CLK_8_1("pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0),
CLK_8_1("pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0),
CLK_8_1("pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0),
CLK_8_1("pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0),
CLK_8_1("pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0),
CLK16_1("pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART),
CLK16_1("pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART),
CLK_8_1("pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
CLK_8_1("pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
CLK16_0("pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
CLK_8_1(0, "pc_i2s1", mux_a_N_audio1_N_p_N_clkm, CLK_SOURCE_I2S1, DCF_HAVE_ENA),
CLK_8_1(0, "pc_i2s2", mux_a_N_audio2_N_p_N_clkm, CLK_SOURCE_I2S2, DCF_HAVE_ENA),
CLK_8_1(0, "pc_spdif_out", mux_a_N_audio_N_p_N_clkm, CLK_SOURCE_SPDIF_OUT, 0),
CLK_8_1(0, "pc_spdif_in", mux_p_c2_c_c3_m, CLK_SOURCE_SPDIF_IN, 0),
CLK_8_1(0, "pc_pwm", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_PWM, 0),
CLK_8_1(0, "pc_spi2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI2, 0),
CLK_8_1(0, "pc_spi3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI3, 0),
CLK16_0(0, "pc_i2c5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C5, 0),
CLK16_0(0, "pc_i2c1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C1, 0),
CLK_8_1(0, "pc_spi1", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI1, 0),
CLK_0_0(0, "pc_disp1", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP1, 0),
CLK_0_0(0, "pc_disp2", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_DISP2, 0),
CLK_8_1(0, "pc_isp", mux_m_c_p_a_c2_c3_clkm_c4, CLK_SOURCE_ISP, 0),
CLK_8_1(0, "pc_vi", mux_m_c2_c_c3_p_N_a_c4, CLK_SOURCE_VI, DCF_IS_VI),
CLK_8_1(0, "pc_sdmmc1", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC1, 0),
CLK_8_1(0, "pc_sdmmc2", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC2, 0),
CLK_8_1(0, "pc_sdmmc4", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC4, 0),
CLK_8_1(0, "pc_vfir", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VFIR, 0),
CLK_8_1(0, "pc_hsi", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HSI, 0),
CLK16_1(0, "pc_uarta", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTA, DCF_IS_UART),
CLK16_1(0, "pc_uartb", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTB, DCF_IS_UART),
CLK_8_1(0, "pc_host1x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HOST1X, DCF_IS_HOST1X),
CLK_8_1(0, "pc_hdmi", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_HDMI, 0),
CLK16_0(0, "pc_i2c2", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C2, 0),
/* EMC 8 */
CLK16_1("pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
CLK_8_1("pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
CLK_8_1("pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
CLK16_0("pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0),
CLK_8_1("pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
CLK16_1("pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART),
CLK_8_1("pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0),
CLK_8_1("pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0),
CLK_8_1("pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0),
CLK_8_1("pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0),
CLK_8_1("pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0),
CLK16_1(0, "pc_uartc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTC, DCF_IS_UART),
CLK_8_1(0, "pc_vi_sensor", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR, 0),
CLK_8_1(0, "pc_spi4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI4, 0),
CLK16_0(0, "pc_i2c3", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C3, 0),
CLK_8_1(0, "pc_sdmmc3", mux_p_c2_c_c3_m_e_clkm, CLK_SOURCE_SDMMC3, 0),
CLK16_1(0, "pc_uartd", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_UARTD, DCF_IS_UART),
CLK_8_1(0, "pc_vde", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_VDE, 0),
CLK_8_1(0, "pc_owr", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_OWR, 0),
CLK_8_1(0, "pc_snor", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_NOR, 0),
CLK_8_1(0, "pc_csite", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_CSITE, 0),
CLK_8_1(0, "pc_i2s0", mux_a_N_audio0_N_p_N_clkm, CLK_SOURCE_I2S0, 0),
/* DTV xxx */
CLK_8_1("pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0),
CLK_8_1("pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0),
CLK_8_1(0, "pc_msenc", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_MSENC, 0),
CLK_8_1(0, "pc_tsec", mux_p_c2_c_c3_m_a_clkm, CLK_SOURCE_TSEC, 0),
/* SPARE2 */
CLK_8_1("pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0),
CLK_8_1("pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0),
CLK_8_1("pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
CLK_8_1("pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
CLK16_0("pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0),
CLK_8_1("pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0),
CLK_8_1("pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0),
CLK_8_1("pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO),
CLK_8_1("pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO),
CLK_8_1("pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO),
CLK_8_1("pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO),
CLK_8_1("pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0),
CLK_8_1("pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0),
CLK_8_1("pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
CLK_8_1("pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0),
CLK_8_1("pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
CLK_8_1("pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0),
CLK_8_1(0, "pc_mselect", mux_p_c2_c_c3_m_clks_clkm, CLK_SOURCE_MSELECT, 0),
CLK_8_1(0, "pc_tsensor", mux_p_c2_c_c3_clkm_N_clks, CLK_SOURCE_TSENSOR, 0),
CLK_8_1(0, "pc_i2s3", mux_a_N_audio3_N_p_N_clkm, CLK_SOURCE_I2S3, DCF_HAVE_ENA),
CLK_8_1(0, "pc_i2s4", mux_a_N_audio4_N_p_N_clkm, CLK_SOURCE_I2S4, DCF_HAVE_ENA),
CLK16_0(0, "pc_i2c4", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C4, 0),
CLK_8_1(0, "pc_spi5", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI5, 0),
CLK_8_1(0, "pc_spi6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_SPI6, 0),
CLK_8_1(0, "pc_audio", mux_sep_audio, CLK_SOURCE_AUDIO, DCF_IS_AUDIO),
CLK_8_1(0, "pc_dam0", mux_sep_audio, CLK_SOURCE_DAM0, DCF_IS_AUDIO),
CLK_8_1(0, "pc_dam1", mux_sep_audio, CLK_SOURCE_DAM1, DCF_IS_AUDIO),
CLK_8_1(0, "pc_dam2", mux_sep_audio, CLK_SOURCE_DAM2, DCF_IS_AUDIO),
CLK_8_1(0, "pc_hda2codec_2x", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA2CODEC_2X, 0),
CLK_8_1(0, "pc_actmon", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_ACTMON, 0),
CLK_8_1(0, "pc_extperiph1", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH1, 0),
CLK_8_1(0, "pc_extperiph2", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH2, 0),
CLK_8_1(0, "pc_extperiph3", mux_a_clks_p_clkm_e, CLK_SOURCE_EXTPERIPH3, 0),
CLK_8_1(0, "pc_i2c_slow", mux_p_c2_c_c3_clks_N_clkm, CLK_SOURCE_I2C_SLOW, 0),
/* SYS */
CLK_8_1("pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0),
CLK_8_1("pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
CLK_8_1("pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, FDS_IS_SATA),
CLK_8_1("pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
CLK_8_1("pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
CLK_8_1("pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0),
CLK_8_1("pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
CLK_8_1("pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
CLK_8_1("pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
CLK_8_1("pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0),
CLK_8_1("pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0),
CLK_8_1("pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0),
CLK_8_1("pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0),
CLK_8_1("pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0),
CLK_8_1("pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0),
CLK_8_1("pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
CLK_8_1("pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
CLK_8_1("pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0),
CLK_8_1("pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),
CLK_8_1("pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),
CLK_8_1("pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0),
CLK_8_1("pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0),
CLK_8_1("pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
CLK16_0("pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0),
CLK_8_1("pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
CLK_8_1("pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0),
CLK_8_1("pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0),
CLK_8_1("pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),
CLK_8_1("pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),
CLK_8_1("pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
CLK_8_1(0, "pc_sor0", mux_p_m_d_a_c_d2_clkm, CLK_SOURCE_SOR0, DCF_IS_SOR0),
CLK_8_1(0, "pc_sata_oob", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA_OOB, 0),
CLK_8_1(0, "pc_sata", mux_p_N_c_N_m_N_clkm, CLK_SOURCE_SATA, FDS_IS_SATA),
CLK_8_1(0, "pc_hda", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_HDA, 0),
CLK_8_1(TEGRA124_CLK_XUSB_HOST_SRC,
"pc_xusb_core_host", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_HOST, 0),
CLK_8_1(TEGRA124_CLK_XUSB_FALCON_SRC,
"pc_xusb_falcon", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_FALCON, 0),
CLK_8_1(TEGRA124_CLK_XUSB_FS_SRC,
"pc_xusb_fs", mux_clkm_N_u48_N_p_N_u480, CLK_SOURCE_XUSB_FS, 0),
CLK_8_1(TEGRA124_CLK_XUSB_DEV_SRC,
"pc_xusb_core_dev", mux_clkm_p_c2_c_c3_refre, CLK_SOURCE_XUSB_CORE_DEV, 0),
CLK_8_1(TEGRA124_CLK_XUSB_SS_SRC,
"pc_xusb_ss", mux_clkm_refe_clks_u480_c_c2_c3_oscdiv, CLK_SOURCE_XUSB_SS, DCF_IS_XUSB_SS),
CLK_8_1(0, "pc_cilab", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILAB, 0),
CLK_8_1(0, "pc_cilcd", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILCD, 0),
CLK_8_1(0, "pc_cile", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_CILE, 0),
CLK_8_1(0, "pc_dsia_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIA_LP, 0),
CLK_8_1(0, "pc_dsib_lp", mux_p_N_c_N_N_N_clkm, CLK_SOURCE_DSIB_LP, 0),
CLK_8_1(0, "pc_entropy", mux_p_clkm_clks_E, CLK_SOURCE_ENTROPY, 0),
CLK_8_1(0, "pc_dvfs_ref", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_REF, DCF_HAVE_ENA),
CLK_8_1(0, "pc_dvfs_soc", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_DVFS_SOC, DCF_HAVE_ENA),
CLK_8_1(0, "pc_traceclkin", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_TRACECLKIN, 0),
CLK_8_1(0, "pc_adx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX, DCF_HAVE_ENA),
CLK_8_1(0, "pc_amx", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX, DCF_HAVE_ENA),
CLK_8_1(0, "pc_emc_latency", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_LATENCY, 0),
CLK_8_1(0, "pc_soc_therm", mux_m_c_p_a_c2_c3, CLK_SOURCE_SOC_THERM, 0),
CLK_8_1(0, "pc_vi_sensor2", mux_m_c2_c_c3_p_N_a, CLK_SOURCE_VI_SENSOR2, 0),
CLK16_0(0, "pc_i2c6", mux_p_c2_c_c3_m_N_clkm, CLK_SOURCE_I2C6, 0),
CLK_8_1(0, "pc_emc_dll", mux_m_c_p_clkm_mud_c2_c3, CLK_SOURCE_EMC_DLL, DCF_IS_EMC_DLL),
CLK_8_1(0, "pc_hdmi_audio", mux_p_c_c2_clkm, CLK_SOURCE_HDMI_AUDIO, 0),
CLK_8_1(0, "pc_clk72mhz", mux_p_c_c2_clkm, CLK_SOURCE_CLK72MHZ, 0),
CLK_8_1(0, "pc_adx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_ADX1, DCF_HAVE_ENA),
CLK_8_1(0, "pc_amx1", mux_a_c2_c_c3_p_N_clkm, CLK_SOURCE_AMX1, DCF_HAVE_ENA),
CLK_8_1(0, "pc_vic", mux_m_c_p_a_c2_c3_clkm, CLK_SOURCE_VIC, DCF_IS_VIC),
};
static int periph_init(struct clknode *clk, device_t dev);
@@ -528,6 +541,7 @@ static clknode_method_t periph_methods[] = {
};
DEFINE_CLASS_1(tegra124_periph, tegra124_periph_class, periph_methods,
sizeof(struct periph_sc), clknode_class);
static int
periph_init(struct clknode *clk, device_t dev)
{
@@ -637,14 +651,13 @@ periph_set_freq(struct clknode *clk, uint64_t fin, uint64_t *fout,
divider++;
if (divider < (1 << sc->div_f_width))
divider = 1 << sc->div_f_width;
divider = 1 << (sc->div_f_width - 1);
if ((*stop != 0) &&
((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
(*fout != (tmp / divider)))
return (ERANGE);
if ((flags & CLK_SET_DRYRUN) == 0) {
if (flags & CLK_SET_DRYRUN) {
if (((flags & (CLK_SET_ROUND_UP | CLK_SET_ROUND_DOWN)) == 0) &&
(*fout != (tmp / divider)))
return (ERANGE);
} else {
DEVICE_LOCK(sc);
MD4(sc, sc->base_reg, sc->div_mask,
(divider - (1 << sc->div_f_width)));
@@ -703,9 +716,9 @@ DEFINE_CLASS_1(tegra124_pgate, tegra124_pgate_class, pgate_methods,
static uint32_t
get_enable_reg(int idx)
{
KASSERT(idx / 32 < nitems(clk_enabale_reg),
KASSERT(idx / 32 < nitems(clk_enable_reg),
("Invalid clock index for enable: %d", idx));
return (clk_enabale_reg[idx / 32]);
return (clk_enable_reg[idx / 32]);
}
static uint32_t
sys/arm/nvidia/tegra124/tegra124_clk_pll.c
+28 -10
View File
@@ -205,6 +205,16 @@ static struct pdiv_table pllu_map[] = {
{0, 0}
};
static struct pdiv_table pllrefe_map[] = {
{1, 0},
{2, 1},
{3, 2},
{4, 3},
{5, 4},
{6, 5},
{0, 0},
};
static struct clk_pll_def pll_clks[] = {
/* PLLM: 880 MHz Clock source for EMC 2x clock */
{
@@ -342,6 +352,7 @@ static struct clk_pll_def pll_clks[] = {
.lock_enable = PLLRE_MISC_LOCK_ENABLE,
.iddq_reg = PLLRE_MISC,
.iddq_mask = 1 << PLLRE_IDDQ_BIT,
.pdiv_table = pllrefe_map,
.mnp_bits = {8, 8, 4, 16},
},
/* PLLE: generate the 100 MHz reference clock for USB 3.0 (spread spectrum) */
@@ -433,14 +444,14 @@ pdiv_to_reg(struct pll_sc *sc, uint32_t p_div)
tbl = sc->pdiv_table;
if (tbl == NULL)
return (ffs(p_div));
return (ffs(p_div) - 1);
while (tbl->divider != 0) {
if (p_div <= tbl->divider)
return (tbl->value);
tbl++;
}
return ~0;
return (0xFFFFFFFF);
}
static uint32_t
@@ -449,15 +460,15 @@ reg_to_pdiv(struct pll_sc *sc, uint32_t reg)
struct pdiv_table *tbl;
tbl = sc->pdiv_table;
if (tbl != NULL) {
while (tbl->divider) {
if (reg == tbl->value)
return (tbl->divider);
tbl++;
}
return (0);
if (tbl == NULL)
return (1 << reg);
while (tbl->divider) {
if (reg == tbl->value)
return (tbl->divider);
tbl++;
}
return (1 << reg);
return (0);
}
static uint32_t
@@ -790,6 +801,7 @@ pllrefe_set_freq(struct pll_sc *sc, uint64_t fin, uint64_t *fout, int flags)
m = 1;
p = 1;
n = *fout * p * m / fin;
dprintf("%s: m: %d, n: %d, p: %d\n", __func__, m, n, p);
return (pll_set_std(sc, fin, fout, flags, m, n, p));
}
@@ -902,6 +914,7 @@ tegra124_pll_set_freq(struct clknode *clknode, uint64_t fin, uint64_t *fout,
rv = ENXIO;
break;
}
return (rv);
}
@@ -921,6 +934,11 @@ tegra124_pll_init(struct clknode *clk, device_t dev)
reg |= sc->lock_enable;
WR4(sc, sc->misc_reg, reg);
}
if (sc->type == PLL_REFE) {
RD4(sc, sc->misc_reg, &reg);
reg &= ~(1 << 29); /* Diasble lock override */
WR4(sc, sc->misc_reg, reg);
}
clknode_init_parent_idx(clk, 0);
return(0);
sys/arm/nvidia/tegra_mc.c
+311
View File
@@ -0,0 +1,311 @@
/*-
* Copyright (c) 2016 Michal Meloun <[email protected]>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* Memory controller driver for Tegra SoCs.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/limits.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/module.h>
#include <sys/resource.h>
#include <machine/bus.h>
#include <machine/resource.h>
#include <sys/rman.h>
#include <dev/extres/clk/clk.h>
#include <dev/ofw/ofw_bus.h>
#include <dev/ofw/ofw_bus_subr.h>
#include "clock_if.h"
#define MC_INTSTATUS 0x000
#define MC_INTMASK 0x004
#define MC_INT_DECERR_MTS (1 << 16)
#define MC_INT_SECERR_SEC (1 << 13)
#define MC_INT_DECERR_VPR (1 << 12)
#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11)
#define MC_INT_INVALID_SMMU_PAGE (1 << 10)
#define MC_INT_ARBITRATION_EMEM (1 << 9)
#define MC_INT_SECURITY_VIOLATION (1 << 8)
#define MC_INT_DECERR_EMEM (1 << 6)
#define MC_INT_INT_MASK (MC_INT_DECERR_MTS | \
MC_INT_SECERR_SEC | \
MC_INT_DECERR_VPR | \
MC_INT_INVALID_APB_ASID_UPDATE | \
MC_INT_INVALID_SMMU_PAGE | \
MC_INT_ARBITRATION_EMEM | \
MC_INT_SECURITY_VIOLATION | \
MC_INT_DECERR_EMEM)
#define MC_ERR_STATUS 0x008
#define MC_ERR_TYPE(x) (((x) >> 28) & 0x7)
#define MC_ERR_TYPE_DECERR_EMEM 2
#define MC_ERR_TYPE_SECURITY_TRUSTZONE 3
#define MC_ERR_TYPE_SECURITY_CARVEOUT 4
#define MC_ERR_TYPE_INVALID_SMMU_PAGE 6
#define MC_ERR_INVALID_SMMU_PAGE_READABLE (1 << 27)
#define MC_ERR_INVALID_SMMU_PAGE_WRITABLE (1 << 26)
#define MC_ERR_INVALID_SMMU_PAGE_NONSECURE (1 << 25)
#define MC_ERR_ADR_HI(x) (((x) >> 20) & 0x3)
#define MC_ERR_SWAP (1 << 18)
#define MC_ERR_SECURITY (1 << 17)
#define MC_ERR_RW (1 << 16)
#define MC_ERR_ADR1(x) (((x) >> 12) & 0x7)
#define MC_ERR_ID(x) (((x) >> 0) & 07F)
#define MC_ERR_ADDR 0x00C
#define MC_EMEM_CFG 0x050
#define MC_EMEM_ADR_CFG 0x054
#define MC_EMEM_NUMDEV(x) (((x) >> 0 ) & 0x1)
#define MC_EMEM_ADR_CFG_DEV0 0x058
#define MC_EMEM_ADR_CFG_DEV1 0x05C
#define EMEM_DEV_DEVSIZE(x) (((x) >> 16) & 0xF)
#define EMEM_DEV_BANKWIDTH(x) (((x) >> 8) & 0x3)
#define EMEM_DEV_COLWIDTH(x) (((x) >> 8) & 0x3)
#define WR4(_sc, _r, _v) bus_write_4((_sc)->mem_res, (_r), (_v))
#define RD4(_sc, _r) bus_read_4((_sc)->mem_res, (_r))
#define LOCK(_sc) mtx_lock(&(_sc)->mtx)
#define UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
#define SLEEP(_sc, timeout) mtx_sleep(sc, &sc->mtx, 0, "tegra_mc", timeout);
#define LOCK_INIT(_sc) \
mtx_init(&_sc->mtx, device_get_nameunit(_sc->dev), "tegra_mc", MTX_DEF)
#define LOCK_DESTROY(_sc) mtx_destroy(&_sc->mtx)
#define ASSERT_LOCKED(_sc) mtx_assert(&_sc->mtx, MA_OWNED)
#define ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->mtx, MA_NOTOWNED)
static struct ofw_compat_data compat_data[] = {
{"nvidia,tegra124-mc", 1},
{NULL, 0}
};
struct tegra_mc_softc {
device_t dev;
struct mtx mtx;
struct resource *mem_res;
struct resource *irq_res;
void *irq_h;
clk_t clk;
};
static char *smmu_err_tbl[16] = {
"reserved", /* 0 */
"reserved", /* 1 */
"DRAM decode", /* 2 */
"Trustzome Security", /* 3 */
"Security carveout", /* 4 */
"reserved", /* 5 */
"Invalid SMMU page", /* 6 */
"reserved", /* 7 */
};
static void
tegra_mc_intr(void *arg)
{
struct tegra_mc_softc *sc;
uint32_t stat, err;
uint64_t addr;
sc = (struct tegra_mc_softc *)arg;
stat = RD4(sc, MC_INTSTATUS);
if ((stat & MC_INT_INT_MASK) == 0) {
WR4(sc, MC_INTSTATUS, stat);
return;
}
device_printf(sc->dev, "Memory Controller Interrupt:\n");
if (stat & MC_INT_DECERR_MTS)
printf(" - MTS carveout violation\n");
if (stat & MC_INT_SECERR_SEC)
printf(" - SEC carveout violation\n");
if (stat & MC_INT_DECERR_VPR)
printf(" - VPR requirements violated\n");
if (stat & MC_INT_INVALID_APB_ASID_UPDATE)
printf(" - ivalid APB ASID update\n");
if (stat & MC_INT_INVALID_SMMU_PAGE)
printf(" - SMMU address translation error\n");
if (stat & MC_INT_ARBITRATION_EMEM)
printf(" - arbitration deadlock-prevention threshold hit\n");
if (stat & MC_INT_SECURITY_VIOLATION)
printf(" - SMMU address translation security error\n");
if (stat & MC_INT_DECERR_EMEM)
printf(" - SMMU address decode error\n");
if ((stat & (MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
MC_INT_DECERR_EMEM)) != 0) {
err = RD4(sc, MC_ERR_STATUS);
addr = RD4(sc, MC_ERR_STATUS);
addr |= (uint64_t)(MC_ERR_ADR_HI(err)) << 32;
printf(" at 0x%012llX [%s %s %s] - %s error.\n",
addr,
stat & MC_ERR_SWAP ? "Swap, " : "",
stat & MC_ERR_SECURITY ? "Sec, " : "",
stat & MC_ERR_RW ? "Write" : "Read",
smmu_err_tbl[MC_ERR_TYPE(err)]);
}
WR4(sc, MC_INTSTATUS, stat);
}
static void
tegra_mc_init_hw(struct tegra_mc_softc *sc)
{
/* Disable and acknowledge all interrupts */
WR4(sc, MC_INTMASK, 0);
WR4(sc, MC_INTSTATUS, MC_INT_INT_MASK);
}
static int
tegra_mc_probe(device_t dev)
{
if (!ofw_bus_status_okay(dev))
return (ENXIO);
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
return (ENXIO);
device_set_desc(dev, "Tegra Memory Controller");
return (BUS_PROBE_DEFAULT);
}
static int
tegra_mc_attach(device_t dev)
{
int rv, rid;
struct tegra_mc_softc *sc;
sc = device_get_softc(dev);
sc->dev = dev;
LOCK_INIT(sc);
/* Get the memory resource for the register mapping. */
rid = 0;
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (sc->mem_res == NULL) {
device_printf(dev, "Cannot map registers.\n");
rv = ENXIO;
goto fail;
}
/* Allocate our IRQ resource. */
rid = 0;
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
RF_ACTIVE);
if (sc->irq_res == NULL) {
device_printf(dev, "Cannot allocate interrupt.\n");
rv = ENXIO;
goto fail;
}
/* OFW resources. */
rv = clk_get_by_ofw_name(dev, 0, "mc", &sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot get mc clock: %d\n", rv);
goto fail;
}
rv = clk_enable(sc->clk);
if (rv != 0) {
device_printf(dev, "Cannot enable clock: %d\n", rv);
goto fail;
}
/* Init hardware. */
tegra_mc_init_hw(sc);
/* Setup interrupt */
rv = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
NULL, tegra_mc_intr, sc, &sc->irq_h);
if (rv) {
device_printf(dev, "Cannot setup interrupt.\n");
goto fail;
}
/* Enable Interrupts */
WR4(sc, MC_INTMASK, MC_INT_INT_MASK);
return (bus_generic_attach(dev));
fail:
if (sc->clk != NULL)
clk_release(sc->clk);
if (sc->irq_h != NULL)
bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
if (sc->irq_res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
if (sc->mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
LOCK_DESTROY(sc);
return (rv);
}
static int
tegra_mc_detach(device_t dev)
{
struct tegra_mc_softc *sc;
sc = device_get_softc(dev);
if (sc->irq_h != NULL)
bus_teardown_intr(dev, sc->irq_res, sc->irq_h);
if (sc->irq_res != NULL)
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->irq_res);
if (sc->mem_res != NULL)
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
LOCK_DESTROY(sc);
return (bus_generic_detach(dev));
}
static device_method_t tegra_mc_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, tegra_mc_probe),
DEVMETHOD(device_attach, tegra_mc_attach),
DEVMETHOD(device_detach, tegra_mc_detach),
DEVMETHOD_END
};
static devclass_t tegra_mc_devclass;
static DEFINE_CLASS_0(mc, tegra_mc_driver, tegra_mc_methods,
sizeof(struct tegra_mc_softc));
DRIVER_MODULE(tegra_mc, simplebus, tegra_mc_driver, tegra_mc_devclass,
NULL, NULL);