Import device-tree files from Linux 6.19

This commit is contained in:
Emmanuel Vadot committed 2026-08-27 09:04:47 +02:00
1 parent 8b46e9538c
commit 93922de2d5
1481 files changed
+104084 -7156

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+1 -1
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@@ -30,7 +30,7 @@ rules:
document-start:
present: true
empty-lines:
max: 3
max: 1
max-end: 1
empty-values:
forbid-in-block-mappings: true
+2 -1
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@@ -32,7 +32,8 @@ find_cmd = $(find_all_cmd) | \
sed 's|^$(srctree)/||' | \
grep -F -e "$(subst :," -e ",$(DT_SCHEMA_FILES))" | \
sed 's|^|$(srctree)/|'
CHK_DT_EXAMPLES := $(patsubst $(srctree)/%.yaml,%.example.dtb, $(shell $(find_cmd)))
CHK_DT_EXAMPLES := $(patsubst $(srctree)/%.yaml,%.example.dtb, \
$(shell $(find_cmd) | xargs grep -l '^examples:'))
quiet_cmd_yamllint = LINT $(src)
cmd_yamllint = ($(find_cmd) | \
+23 -1
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@@ -31,7 +31,9 @@ properties:
- description: Mercury+ AA1 boards
items:
- enum:
- enclustra,mercury-pe1
- enclustra,mercury-aa1-pe1
- enclustra,mercury-aa1-pe3
- enclustra,mercury-aa1-st1
- google,chameleon-v3
- const: enclustra,mercury-aa1
- const: altr,socfpga-arria10
@@ -52,6 +54,26 @@ properties:
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Mercury SA1 boards
items:
- enum:
- enclustra,mercury-sa1-pe1
- enclustra,mercury-sa1-pe3
- enclustra,mercury-sa1-st1
- const: enclustra,mercury-sa1
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Mercury+ SA2 boards
items:
- enum:
- enclustra,mercury-sa2-pe1
- enclustra,mercury-sa2-pe3
- enclustra,mercury-sa2-st1
- const: enclustra,mercury-sa2
- const: altr,socfpga-cyclone5
- const: altr,socfpga
- description: Stratix 10 boards
items:
- enum:
+10 -10
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@@ -27,17 +27,17 @@ properties:
additionalProperties: false
properties:
"#address-cells":
'#address-cells':
const: 1
"#size-cells":
'#size-cells':
const: 0
patternProperties:
"^osc[0-9]$":
'^osc[0-9]$':
type: object
"^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$":
'^[a-z0-9,_]+(clk|pll|clk_gate|clk_divided)(@[a-f0-9]+)?$':
type: object
$ref: '#/$defs/clock-props'
unevaluatedProperties: false
@@ -58,14 +58,14 @@ properties:
minItems: 1
maxItems: 5
"#address-cells":
'#address-cells':
const: 1
"#size-cells":
'#size-cells':
const: 0
patternProperties:
"^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$":
'^[a-z0-9,_]+(clk|pll)(@[a-f0-9]+)?$':
type: object
$ref: '#/$defs/clock-props'
unevaluatedProperties: false
@@ -86,11 +86,11 @@ properties:
required:
- compatible
- clocks
- "#clock-cells"
- '#clock-cells'
required:
- compatible
- "#clock-cells"
- '#clock-cells'
required:
- compatible
@@ -104,7 +104,7 @@ $defs:
reg:
maxItems: 1
"#clock-cells":
'#clock-cells':
const: 0
clk-gate:
+24
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@@ -0,0 +1,24 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/amd,seattle.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: AMD Seattle SoC Platforms
maintainers:
- Suravee Suthikulpanit <[email protected]>
- Tom Lendacky <[email protected]>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Boards with AMD Seattle SoC
items:
- const: amd,seattle-overdrive
- const: amd,seattle
additionalProperties: true
...
+1
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@@ -134,6 +134,7 @@ properties:
- libretech,aml-s912-pc
- minix,neo-u9h
- nexbox,a1
- oranth,tx9-pro
- tronsmart,vega-s96
- ugoos,am3
- videostrong,gxm-kiii-pro
@@ -34,6 +34,9 @@ properties:
- amlogic,a4-ao-secure
- amlogic,c3-ao-secure
- amlogic,s4-ao-secure
- amlogic,s6-ao-secure
- amlogic,s7-ao-secure
- amlogic,s7d-ao-secure
- amlogic,t7-ao-secure
- const: amlogic,meson-gx-ao-secure
- const: syscon
+28
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@@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/apm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: APM X-Gene SoC Platforms
maintainers:
- Khuong Dinh <[email protected]>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Boards with X-Gene1 Soc
items:
- const: apm,mustang
- const: apm,xgene-storm
- description: Boards with X-Gene2 SoC
items:
- const: apm,merlin
- const: apm,xgene-shadowcat
additionalProperties: true
...
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Integrator Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |+
These were the first ARM platforms officially supported by ARM Ltd.
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM RealView Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |+
The ARM RealView series of reference designs were built to explore the Arm11,
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Snoop Control Unit (SCU)
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
As part of the MPCore complex, Cortex-A5 and Cortex-A9 are provided
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Arm Versatile system registers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description:
This is a system control registers block, providing multiple low level
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Boards
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |+
The ARM Versatile boards are two variants of ARM926EJ-S evaluation boards
+1 -1
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@@ -8,7 +8,7 @@ title: ARM Versatile Express and Juno Boards
maintainers:
- Sudeep Holla <[email protected]>
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |+
ARM's Versatile Express platform were built as reference designs for exploring
+3
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@@ -93,7 +93,10 @@ properties:
- facebook,minerva-cmc
- facebook,santabarbara-bmc
- facebook,yosemite4-bmc
- facebook,yosemite5-bmc
- ibm,balcones-bmc
- ibm,blueridge-bmc
- ibm,bonnell-bmc
- ibm,everest-bmc
- ibm,fuji-bmc
- ibm,rainier-bmc
+31
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@@ -0,0 +1,31 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/bst.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: BST platforms
description:
Black Sesame Technologies (BST) is a semiconductor company that produces
automotive-grade system-on-chips (SoCs) for intelligent driving, focusing
on computer vision and AI capabilities. The BST C1200 family includes SoCs
for ADAS (Advanced Driver Assistance Systems) and autonomous driving
applications.
maintainers:
- Ge Gordon <[email protected]>
properties:
$nodename:
const: '/'
compatible:
oneOf:
- description: BST C1200 CDCU1.0 ADAS 4C2G board
items:
- const: bst,c1200-cdcu1.0-adas-4c2g
- const: bst,c1200
additionalProperties: true
...
+25 -1
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@@ -1105,12 +1105,14 @@ properties:
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw75xx-2x # i.MX8MP Gateworks Board
- gateworks,imx8mp-gw82xx-2x # i.MX8MP Gateworks Board
- gocontroll,moduline-display # GOcontroll Moduline Display controller
- prt,prt8ml # Protonic PRT8ML
- skov,imx8mp-skov-basic # SKOV i.MX8MP baseboard without frontplate
- skov,imx8mp-skov-revb-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revb-lt6 # SKOV i.MX8MP climate control with 7” panel
- skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel
- skov,imx8mp-skov-revc-hdmi # SKOV i.MX8MP climate control without panel
- skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate
- skov,imx8mp-skov-revc-jutouch-jt101tm023 # SKOV i.MX8MP climate control with 10" JuTouch panel
- skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel
- ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board
- ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board
@@ -1161,6 +1163,14 @@ properties:
- const: engicam,icore-mx8mp # i.MX8MP Engicam i.Core MX8M Plus SoM
- const: fsl,imx8mp
- description: Ka-Ro TX8P-ML81 SoM based boards
items:
- enum:
- gocontroll,moduline-display
- gocontroll,moduline-display-106
- const: karo,tx8p-ml81
- const: fsl,imx8mp
- description: Kontron i.MX8MP OSM-S SoM based Boards
items:
- const: kontron,imx8mp-bl-osm-s # Kontron BL i.MX8MP OSM-S Board
@@ -1430,6 +1440,7 @@ properties:
- enum:
- fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board
- fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board
- toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK)
- const: fsl,imx95
- description: PHYTEC i.MX 95 FPSC based Boards
@@ -1439,6 +1450,12 @@ properties:
- const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC
- const: fsl,imx95
- description: Toradex Boards with SMARC iMX95 Modules
items:
- const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board
- const: toradex,smarc-imx95 # Toradex SMARC iMX95 Module
- const: fsl,imx95
- description: i.MXRT1050 based Boards
items:
- enum:
@@ -1492,6 +1509,13 @@ properties:
- const: tq,imx93-tqma9352 # TQ-Systems GmbH i.MX93 TQMa93xxCA/LA SOM
- const: fsl,imx93
- description: PHYTEC phyCORE-i.MX91 SoM based boards
items:
- enum:
- phytec,imx91-phyboard-segin # phyBOARD-Segin with i.MX91
- const: phytec,imx91-phycore-som # phyCORE-i.MX91 SoM
- const: fsl,imx91
- description: PHYTEC phyCORE-i.MX93 SoM based boards
items:
- enum:
+1 -1
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@@ -20,7 +20,7 @@ description: |
Many of the IP blocks used in the SoC comes from Faraday Technology.
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
properties:
$nodename:
+7
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@@ -21,10 +21,17 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- const: intel,socfpga-agilex
- description: Agilex3 boards
items:
- enum:
- intel,socfpga-agilex3-socdk
- const: intel,socfpga-agilex3
- const: intel,socfpga-agilex5
- description: Agilex5 boards
items:
- enum:
- intel,socfpga-agilex5-socdk
- intel,socfpga-agilex5-socdk-013b
- intel,socfpga-agilex5-socdk-nand
- const: intel,socfpga-agilex5
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
properties:
$nodename:
+28
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@@ -0,0 +1,28 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/lge.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LG Electronics SoC Platforms
maintainers:
- Chanho Min <[email protected]>
properties:
$nodename:
const: "/"
compatible:
oneOf:
- description: Boards with LG1312 Soc
items:
- const: lge,lg1312-ref
- const: lge,lg1312
- description: Boards with LG1313 SoC
items:
- const: lge,lg1313-ref
- const: lge,lg1313
additionalProperties: true
...
+8
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@@ -38,6 +38,7 @@ properties:
- const: mediatek,mt6580
- items:
- enum:
- alcatel,yarisxl
- prestigio,pmt5008-3g
- const: mediatek,mt6582
- items:
@@ -113,6 +114,12 @@ properties:
- const: bananapi,bpi-r4-2g5
- const: bananapi,bpi-r4
- const: mediatek,mt7988a
- items:
- enum:
- bananapi,bpi-r4-pro-4e
- bananapi,bpi-r4-pro-8x
- const: bananapi,bpi-r4-pro
- const: mediatek,mt7988a
- items:
- enum:
- mediatek,mt8127-moose
@@ -445,6 +452,7 @@ properties:
- enum:
- kontron,3-5-sbc-i1200
- mediatek,mt8395-evk
- mediatek,mt8395-evk-ufs
- radxa,nio-12l
- const: mediatek,mt8395
- const: mediatek,mt8195
-1
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@@ -163,7 +163,6 @@ examples:
method = "smc";
};
- |+
// Case 3: PSCI v0.2 and PSCI v0.1.
+20 -3
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@@ -36,9 +36,12 @@ properties:
$nodename:
pattern: "^tpdm(@[0-9a-f]+)$"
compatible:
items:
- const: qcom,coresight-tpdm
- const: arm,primecell
oneOf:
- items:
- const: qcom,coresight-static-tpdm
- items:
- const: qcom,coresight-tpdm
- const: arm,primecell
reg:
maxItems: 1
@@ -147,4 +150,18 @@ examples:
};
};
};
turing-llm-tpdm {
compatible = "qcom,coresight-static-tpdm";
qcom,cmb-element-bits = <32>;
out-ports {
port {
turing_llm_tpdm_out: endpoint {
remote-endpoint = <&turing0_funnel_in1>;
};
};
};
};
...
+16 -1
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@@ -88,6 +88,7 @@ properties:
- items:
- enum:
- asus,z00t
- huawei,kiwi
- longcheer,l9100
- samsung,a7
@@ -191,6 +192,11 @@ properties:
- xiaomi,riva
- const: qcom,msm8917
- items:
- enum:
- xiaomi,land
- const: qcom,msm8937
- items:
- enum:
- flipkart,rimob
@@ -340,6 +346,7 @@ properties:
- particle,tachyon
- qcom,qcm6490-idp
- qcom,qcs6490-rb3gen2
- radxa,dragon-q6a
- shift,otter
- const: qcom,qcm6490
@@ -893,6 +900,7 @@ properties:
- items:
- enum:
- huawei,planck
- lenovo,yoga-c630
- lg,judyln
- lg,judyp
@@ -1083,7 +1091,13 @@ properties:
- items:
- enum:
- asus,zenbook-a14-ux3407qa
- asus,zenbook-a14-ux3407qa-lcd
- asus,zenbook-a14-ux3407qa-oled
- const: asus,zenbook-a14-ux3407qa
- const: qcom,x1p42100
- items:
- enum:
- hp,omnibook-x14-fe1
- lenovo,thinkbook-16
- qcom,x1p42100-crd
@@ -1167,6 +1181,7 @@ allOf:
- qcom,apq8094
- qcom,apq8096
- qcom,msm8917
- qcom,msm8937
- qcom,msm8939
- qcom,msm8953
- qcom,msm8956
+33 -6
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@@ -15,6 +15,11 @@ properties:
compatible:
oneOf:
- description: 100ASK DshanPi A1 board
items:
- const: 100ask,dshanpi-a1
- const: rockchip,rk3576
- description: 96boards RK3399 Ficus (ROCK960 Enterprise Edition)
items:
- const: vamrs,ficus
@@ -25,6 +30,12 @@ properties:
- const: vamrs,rock960
- const: rockchip,rk3399
- description: 9Tripod X3568 series board
items:
- enum:
- 9tripod,x3568-v4
- const: rockchip,rk3568
- description: Amarula Vyasa RK3288
items:
- const: amarula,vyasa-rk3288
@@ -78,13 +89,17 @@ properties:
- description: Asus Tinker board
items:
- const: asus,rk3288-tinker
- enum:
- asus,rk3288-tinker
- asus,rk3288-tinker-s
- const: rockchip,rk3288
- description: Asus Tinker board S
- description: Asus Tinker Board 3/3S
items:
- const: asus,rk3288-tinker-s
- const: rockchip,rk3288
- enum:
- asus,rk3566-tinker-board-3
- asus,rk3566-tinker-board-3s
- const: rockchip,rk3566
- description: Beelink A1
items:
@@ -330,6 +345,11 @@ properties:
- friendlyarm,nanopi-r6s
- const: rockchip,rk3588s
- description: FriendlyElec NanoPi R76S
items:
- const: friendlyarm,nanopi-r76s
- const: rockchip,rk3576
- description: FriendlyElec NanoPi Zero2
items:
- const: friendlyarm,nanopi-zero2
@@ -748,6 +768,11 @@ properties:
- const: lckfb,tspi-rk3566
- const: rockchip,rk3566
- description: LinkEase EasePi R1
items:
- const: linkease,easepi-r1
- const: rockchip,rk3568
- description: Luckfox Core3576 Module based boards
items:
- enum:
@@ -868,9 +893,11 @@ properties:
- const: prt,mecsbc
- const: rockchip,rk3568
- description: QNAP TS-433-4G 4-Bay NAS
- description: QNAP TS-x33 NAS devices
items:
- const: qnap,ts433
- enum:
- qnap,ts233
- qnap,ts433
- const: rockchip,rk3568
- description: Radxa Compute Module 3 (CM3)
+5
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@@ -189,6 +189,11 @@ properties:
- nvidia,p2371-2180
- nvidia,p2571
- nvidia,p2894-0050-a08
- nvidia,p3450-0000
- const: nvidia,tegra210
- items:
- const: nvidia,p3541-0000
- const: nvidia,p3450-0000
- const: nvidia,tegra210
- description: Jetson TX2 Developer Kit
items:
+15
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@@ -37,6 +37,12 @@ properties:
- const: phytec,am62a-phycore-som
- const: ti,am62a7
- description: K3 AM62L3 SoC and Boards
items:
- enum:
- ti,am62l3-evm
- const: ti,am62l3
- description: K3 AM62P5 SoC and Boards
items:
- enum:
@@ -158,6 +164,14 @@ properties:
- ti,am654-evm
- const: ti,am654
- description: K3 AM69 SoC Toradex Aquila Modules and Carrier Boards
items:
- enum:
- toradex,aquila-am69-clover # Aquila AM69 Module on Clover Board
- toradex,aquila-am69-dev # Aquila AM69 Module on Aquila Development Board
- const: toradex,aquila-am69 # Aquila AM69 Module
- const: ti,j784s4
- description: K3 J7200 SoC
oneOf:
- const: ti,j7200
@@ -194,6 +208,7 @@ properties:
items:
- enum:
- beagle,am67a-beagley-ai
- kontron,sa67 # Kontron SMARC-sAM67 board
- ti,j722s-evm
- const: ti,j722s
+7
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@@ -129,6 +129,13 @@ properties:
- const: phytec,am335x-phycore-som
- const: ti,am33xx
- description: TQ-Systems TQMa335x[L] SoM
items:
- enum:
- tq,tqma3359-mba335x # MBa335x carrier board
- const: tq,tqma3359
- const: ti,am33xx
- description: TI OMAP4430 SoC based platforms
items:
- enum:
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ux500 platforms
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
properties:
$nodename:
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Generic Parallel ATA Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description:
Generic Parallel ATA controllers supporting PIO modes only.
+1 -1
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@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cortina Systems Gemini SATA Bridge
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
The Gemini SATA bridge in a SoC-internal PATA to SATA bridge that
+79
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@@ -0,0 +1,79 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/ata/eswin,eic7700-ahci.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Eswin EIC7700 SoC SATA Controller
maintainers:
- Yulin Lu <[email protected]>
- Huan He <[email protected]>
description:
AHCI SATA controller embedded into the EIC7700 SoC is based on the DWC AHCI
SATA v5.00a IP core.
select:
properties:
compatible:
const: eswin,eic7700-ahci
required:
- compatible
allOf:
- $ref: snps,dwc-ahci-common.yaml#
properties:
compatible:
items:
- const: eswin,eic7700-ahci
- const: snps,dwc-ahci
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: pclk
- const: aclk
resets:
maxItems: 1
reset-names:
const: arst
ports-implemented:
const: 1
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- phys
- phy-names
- ports-implemented
unevaluatedProperties: false
examples:
- |
sata@50420000 {
compatible = "eswin,eic7700-ahci", "snps,dwc-ahci";
reg = <0x50420000 0x10000>;
interrupt-parent = <&plic>;
interrupts = <58>;
clocks = <&clock 171>, <&clock 186>;
clock-names = "pclk", "aclk";
phys = <&sata_phy>;
phy-names = "sata-phy";
ports-implemented = <0x1>;
resets = <&reset 96>;
reset-names = "arst";
};
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday Technology FTIDE010 PATA controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
This controller is the first Faraday IDE interface block, used in the
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx CompactFlash Card Controller
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
The IXP4xx network processors have a CompactFlash interface that presents
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Parallel AT attachment (PATA) controllers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
This document defines device tree properties common to most Parallel
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for Serial AT attachment (SATA) controllers
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
This document defines device tree properties common to most Serial
+4
View File
@@ -33,6 +33,10 @@ properties:
- description: SPEAr1340 AHCI SATA device
const: snps,spear-ahci
iommus:
minItems: 1
maxItems: 3
patternProperties:
"^sata-port@[0-9a-e]$":
$ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Versatile Character LCD
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
- Rob Herring <[email protected]>
description:
+58
View File
@@ -22,6 +22,13 @@ properties:
- fsl,lx2160aqds-fpga
- const: fsl,fpga-qixis-i2c
- const: simple-mfd
- const: fsl,lx2160ardb-fpga
"#address-cells":
const: 1
"#size-cells":
const: 0
interrupts:
maxItems: 1
@@ -32,10 +39,37 @@ properties:
mux-controller:
$ref: /schemas/mux/reg-mux.yaml
patternProperties:
"^gpio@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
enum:
- fsl,lx2160ardb-fpga-gpio-sfp
required:
- compatible
- reg
allOf:
- if:
properties:
compatible:
contains:
enum:
- fsl,lx2160ardb-fpga
then:
required:
- "#address-cells"
- "#size-cells"
else:
properties:
"#address-cells": false
"#size-cells": false
additionalProperties: false
examples:
@@ -68,3 +102,27 @@ examples:
};
};
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
board-control@66 {
compatible = "fsl,lx2160ardb-fpga";
reg = <0x66>;
#address-cells = <1>;
#size-cells = <0>;
gpio@19 {
compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
reg = <0x19>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names =
"SFP2_TX_EN", "",
"", "",
"SFP2_RX_LOS", "SFP2_TX_FAULT",
"", "SFP2_MOD_ABS";
};
};
};
+10
View File
@@ -57,6 +57,16 @@ patternProperties:
'^mdio-mux@[a-f0-9,]+$':
$ref: /schemas/net/mdio-mux-mmioreg.yaml
'^gpio@[0-9a-f]+$':
type: object
additionalProperties: true
properties:
compatible:
contains:
enum:
- fsl,ls1046aqds-fpga-gpio-stat-pres2
required:
- compatible
- reg
+1 -1
View File
@@ -43,7 +43,7 @@ properties:
maximum: 20000000
patternProperties:
"^.*@[0-9a-fA-F]+$":
"@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
+94
View File
@@ -0,0 +1,94 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/cznic,moxtet.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Turris Moxtet SPI bus
maintainers:
- Marek Behún <[email protected]>
description: >
Turris Mox module status and configuration bus (over SPI)
The driver finds the devices connected to the bus by itself, but it may be
needed to reference some of them from other parts of the device tree. In that
case the devices can be defined as subnodes of the moxtet node.
properties:
compatible:
const: cznic,moxtet
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 0
spi-cpol: true
spi-cpha: true
spi-max-frequency: true
interrupt-controller: true
"#interrupt-cells":
const: 1
interrupts:
maxItems: 1
reset-gpios:
maxItems: 1
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
- spi-cpol
- spi-cpha
- interrupts
- interrupt-controller
- "#interrupt-cells"
additionalProperties:
type: object
required:
- reg
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
spi {
#address-cells = <1>;
#size-cells = <0>;
moxtet@1 {
compatible = "cznic,moxtet";
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
spi-max-frequency = <10000000>;
spi-cpol;
spi-cpha;
interrupt-controller;
#interrupt-cells = <1>;
interrupt-parent = <&gpiosb>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
gpio@0 {
compatible = "cznic,moxtet-gpio";
gpio-controller;
#gpio-cells = <2>;
reg = <0>;
};
};
};
@@ -70,7 +70,7 @@ properties:
- const: ahb
patternProperties:
"^.*@[0-9a-f]+$":
"@[0-9a-f]+$":
description: Devices attached to the bus
type: object
+1 -1
View File
@@ -44,7 +44,7 @@ properties:
Contains the firewall ID associated to the peripheral.
patternProperties:
"^.*@[0-9a-f]+$":
"@[0-9a-f]+$":
description: Peripherals
type: object
+7 -3
View File
@@ -33,14 +33,18 @@ select:
properties:
compatible:
contains:
const: st,stm32mp25-rifsc
enum:
- st,stm32mp21-rifsc
- st,stm32mp25-rifsc
required:
- compatible
properties:
compatible:
items:
- const: st,stm32mp25-rifsc
- enum:
- st,stm32mp21-rifsc
- st,stm32mp25-rifsc
- const: simple-bus
reg:
@@ -60,7 +64,7 @@ properties:
Contains the firewall ID associated to the peripheral.
patternProperties:
"^.*@[0-9a-f]+$":
"@[0-9a-f]+$":
description: Peripherals
type: object
+2
View File
@@ -21,6 +21,7 @@ properties:
compatible:
enum:
- qcom,ipq5424-llcc
- qcom,kaanapali-llcc
- qcom,qcs615-llcc
- qcom,qcs8300-llcc
- qcom,qdu1000-llcc
@@ -272,6 +273,7 @@ allOf:
compatible:
contains:
enum:
- qcom,kaanapali-llcc
- qcom,sm8450-llcc
- qcom,sm8550-llcc
- qcom,sm8650-llcc
+5
View File
@@ -48,6 +48,11 @@ properties:
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
- items:
- const: microchip,pic64gx-ccache
- const: microchip,mpfs-ccache
- const: sifive,fu540-c000-ccache
- const: cache
cache-block-size:
const: 64
+1 -2
View File
@@ -64,8 +64,6 @@ allOf:
reg:
minItems: 2
'#reset-cells': false
- if:
properties:
compatible:
@@ -85,6 +83,7 @@ examples:
reg = <0x1fa20000 0x400>,
<0x1fb00000 0x1000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
- |
@@ -132,7 +132,6 @@ examples:
"ahb_mp", "ahb_mali400";
};
- |
clk@1c20068 {
#clock-cells = <1>;
+72
View File
@@ -0,0 +1,72 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/fsl,imx8ulp-sim-lpav.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP i.MX8ULP LPAV System Integration Module (SIM)
maintainers:
- Laurentiu Mihalcea <[email protected]>
description:
The i.MX8ULP LPAV subsystem contains a block control module known as
SIM LPAV, which offers functionalities such as clock gating or reset
line assertion/de-assertion.
properties:
compatible:
const: fsl,imx8ulp-sim-lpav
reg:
maxItems: 1
clocks:
maxItems: 3
clock-names:
items:
- const: bus
- const: core
- const: plat
'#clock-cells':
const: 1
'#reset-cells':
const: 1
mux-controller:
$ref: /schemas/mux/reg-mux.yaml#
required:
- compatible
- reg
- clocks
- clock-names
- '#clock-cells'
- '#reset-cells'
- mux-controller
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8ulp-clock.h>
clock-controller@2da50000 {
compatible = "fsl,imx8ulp-sim-lpav";
reg = <0x2da50000 0x10000>;
clocks = <&cgc2 IMX8ULP_CLK_LPAV_BUS_DIV>,
<&cgc2 IMX8ULP_CLK_HIFI_DIVCORE>,
<&cgc2 IMX8ULP_CLK_HIFI_DIVPLAT>;
clock-names = "bus", "core", "plat";
#clock-cells = <1>;
#reset-cells = <1>;
mux-controller {
compatible = "reg-mux";
#mux-control-cells = <1>;
mux-reg-masks = <0x8 0x00000200>;
};
};
+3
View File
@@ -46,6 +46,9 @@ properties:
"#clock-cells":
const: 1
power-domains:
maxItems: 1
reg:
maxItems: 1
+54
View File
@@ -0,0 +1,54 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,ap80x-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada AP80x System Controller Clocks
maintainers:
- Gregory Clement <[email protected]>
- Miquel Raynal <[email protected]>
description: >
The AP806/AP807 is one of the two core HW blocks of the Marvell Armada
7K/8K/931x SoCs. It contains system controllers, which provide several
registers giving access to numerous features: clocks, pin-muxing and many
other SoC configuration items.
properties:
compatible:
enum:
- marvell,ap806-clock
- marvell,ap806-cpu-clock
- marvell,ap807-clock
- marvell,ap807-cpu-clock
reg:
maxItems: 1
"#clock-cells":
const: 1
clocks:
items:
- description: cluster 0 parent clock phandle
- description: cluster 1 parent clock phandle
required:
- compatible
- "#clock-cells"
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- marvell,ap806-cpu-clock
- marvell,ap807-cpu-clock
then:
required:
- clocks
+70
View File
@@ -0,0 +1,70 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/marvell,cp110-clock.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Marvell Armada CP110 System Controller Clocks
maintainers:
- Gregory Clement <[email protected]>
- Miquel Raynal <[email protected]>
description: >
The CP110 is one of the two core HW blocks of the Marvell Armada 7K/8K/931x
SoCs. It contains system controllers, which provide several registers giving
access to numerous features: clocks, pin-muxing and many other SoC
configuration items.
properties:
compatible:
const: marvell,cp110-clock
"#clock-cells":
const: 2
description: >
The first cell must be 0 or 1. 0 for the core clocks and 1 for the
gateable clocks. The second cell identifies the particular core clock or
gateable clocks.
The following clocks are available:
- Core clocks
- 0 0 APLL
- 0 1 PPv2 core
- 0 2 EIP
- 0 3 Core
- 0 4 NAND core
- 0 5 SDIO core
- Gateable clocks
- 1 0 Audio
- 1 1 Comm Unit
- 1 2 NAND
- 1 3 PPv2
- 1 4 SDIO
- 1 5 MG Domain
- 1 6 MG Core
- 1 7 XOR1
- 1 8 XOR0
- 1 9 GOP DP
- 1 11 PCIe x1 0
- 1 12 PCIe x1 1
- 1 13 PCIe x4
- 1 14 PCIe / XOR
- 1 15 SATA
- 1 16 SATA USB
- 1 17 Main
- 1 18 SD/MMC/GOP
- 1 21 Slow IO (SPI, NOR, BootROM, I2C, UART)
- 1 22 USB3H0
- 1 23 USB3H1
- 1 24 USB3 Device
- 1 25 EIP150
- 1 26 EIP197
required:
- compatible
- "#clock-cells"
additionalProperties: false
+22 -14
View File
@@ -22,16 +22,23 @@ properties:
const: microchip,mpfs-clkcfg
reg:
items:
- description: |
clock config registers:
These registers contain enable, reset & divider tables for the, cpu,
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
for the peripheral clocks.
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
oneOf:
- items:
- description: |
clock config registers:
These registers contain enable, reset & divider tables for the, cpu,
axi, ahb and rtc/mtimer reference clocks as well as enable and reset
for the peripheral clocks.
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
deprecated: true
- items:
- description: |
mss pll dri registers:
Block of registers responsible for dynamic reconfiguration of the mss
pll
clocks:
maxItems: 1
@@ -69,11 +76,12 @@ examples:
- |
#include <dt-bindings/clock/microchip,mpfs-clock.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
clkcfg: clock-controller@20002000 {
#address-cells = <1>;
#size-cells = <1>;
clkcfg: clock-controller@3E001000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>;
reg = <0x3E001000 0x1000>;
clocks = <&ref>;
#clock-cells = <1>;
};
+4 -4
View File
@@ -37,7 +37,7 @@ properties:
'#clock-cells':
const: 1
"#reset-cells":
'#reset-cells':
const: 1
nvidia,external-memory-controller:
@@ -46,7 +46,7 @@ properties:
phandle of the external memory controller node
patternProperties:
"^emc-timings-[0-9]+$":
'^emc-timings-[0-9]+$':
type: object
properties:
nvidia,ram-code:
@@ -56,7 +56,7 @@ patternProperties:
this timing set is used for
patternProperties:
"^timing-[0-9]+$":
'^timing-[0-9]+$':
type: object
properties:
clock-frequency:
@@ -94,7 +94,7 @@ required:
- compatible
- reg
- '#clock-cells'
- "#reset-cells"
- '#reset-cells'
additionalProperties: false
+3 -3
View File
@@ -39,11 +39,11 @@ properties:
'#clock-cells':
const: 1
"#reset-cells":
'#reset-cells':
const: 1
patternProperties:
"^(sclk)|(pll-[cem])$":
'^(sclk)|(pll-[cem])$':
type: object
properties:
compatible:
@@ -76,7 +76,7 @@ required:
- compatible
- reg
- '#clock-cells'
- "#reset-cells"
- '#reset-cells'
additionalProperties: false
+55 -8
View File
@@ -4,7 +4,7 @@
$id: http://devicetree.org/schemas/clock/qcom,ipq9574-nsscc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574
title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ9574 and IPQ5424
maintainers:
- Bjorn Andersson <[email protected]>
@@ -12,21 +12,29 @@ maintainers:
description: |
Qualcomm networking sub system clock control module provides the clocks,
resets on IPQ9574
resets on IPQ9574 and IPQ5424
See also::
See also:
include/dt-bindings/clock/qcom,ipq5424-nsscc.h
include/dt-bindings/clock/qcom,ipq9574-nsscc.h
include/dt-bindings/reset/qcom,ipq5424-nsscc.h
include/dt-bindings/reset/qcom,ipq9574-nsscc.h
properties:
compatible:
const: qcom,ipq9574-nsscc
enum:
- qcom,ipq5424-nsscc
- qcom,ipq9574-nsscc
clocks:
items:
- description: Board XO source
- description: CMN_PLL NSS 1200MHz (Bias PLL cc) clock source
- description: CMN_PLL PPE 353MHz (Bias PLL ubi nc) clock source
- description: CMN_PLL NSS (Bias PLL cc) clock source. This clock rate
can vary for different IPQ SoCs. For example, it is 1200 MHz on the
IPQ9574 and 300 MHz on the IPQ5424.
- description: CMN_PLL PPE (Bias PLL ubi nc) clock source. The clock
rate can vary for different IPQ SoCs. For example, it is 353 MHz
on the IPQ9574 and 375 MHz on the IPQ5424.
- description: GCC GPLL0 OUT AUX clock source
- description: Uniphy0 NSS Rx clock source
- description: Uniphy0 NSS Tx clock source
@@ -42,8 +50,12 @@ properties:
clock-names:
items:
- const: xo
- const: nss_1200
- const: ppe_353
- enum:
- nss_1200
- nss
- enum:
- ppe_353
- ppe
- const: gpll0_out
- const: uniphy0_rx
- const: uniphy0_tx
@@ -60,6 +72,40 @@ required:
allOf:
- $ref: qcom,gcc.yaml#
- if:
properties:
compatible:
const: qcom,ipq9574-nsscc
then:
properties:
clock-names:
items:
- const: xo
- const: nss_1200
- const: ppe_353
- const: gpll0_out
- const: uniphy0_rx
- const: uniphy0_tx
- const: uniphy1_rx
- const: uniphy1_tx
- const: uniphy2_rx
- const: uniphy2_tx
- const: bus
else:
properties:
clock-names:
items:
- const: xo
- const: nss
- const: ppe
- const: gpll0_out
- const: uniphy0_rx
- const: uniphy0_tx
- const: uniphy1_rx
- const: uniphy1_tx
- const: uniphy2_rx
- const: uniphy2_tx
- const: bus
unevaluatedProperties: false
@@ -94,5 +140,6 @@ examples:
"bus";
#clock-cells = <1>;
#reset-cells = <1>;
#interconnect-cells = <1>;
};
...
+1 -1
View File
@@ -8,7 +8,7 @@ title: Qualcomm RPM Clock Controller
maintainers:
- Bjorn Andersson <[email protected]>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Krzysztof Kozlowski <krzk@kernel.org>
description: |
The clock enumerators are defined in <dt-bindings/clock/qcom,rpmcc.h> and
+1
View File
@@ -18,6 +18,7 @@ properties:
compatible:
enum:
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
+4 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Video Clock & Reset Controller on SM8450
maintainers:
- Taniya Das <quic_tdas@quicinc.com>
- Taniya Das <[email protected].com>
- Jagadeesh Kona <[email protected]>
description: |
@@ -17,6 +17,7 @@ description: |
See also:
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
properties:
compatible:
@@ -25,6 +26,7 @@ properties:
- qcom,sm8475-videocc
- qcom,sm8550-videocc
- qcom,sm8650-videocc
- qcom,sm8750-videocc
- qcom,x1e80100-videocc
clocks:
@@ -61,6 +63,7 @@ allOf:
enum:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
then:
required:
- required-opps
+1
View File
@@ -25,6 +25,7 @@ properties:
items:
- enum:
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
+6 -2
View File
@@ -13,11 +13,15 @@ description: |
Qualcomm global clock control module provides the clocks, resets and power
domains on SM8750
See also: include/dt-bindings/clock/qcom,sm8750-gcc.h
See also:
include/dt-bindings/clock/qcom,kaanapali-gcc.h
include/dt-bindings/clock/qcom,sm8750-gcc.h
properties:
compatible:
const: qcom,sm8750-gcc
enum:
- qcom,kaanapali-gcc
- qcom,sm8750-gcc
clocks:
items:
+58 -4
View File
@@ -32,9 +32,36 @@ properties:
- description: PCIe 5 pipe clock
- description: PCIe 6a pipe clock
- description: PCIe 6b pipe clock
- description: USB QMP Phy 0 clock source
- description: USB QMP Phy 1 clock source
- description: USB QMP Phy 2 clock source
- description: USB4_0 QMPPHY clock source
- description: USB4_1 QMPPHY clock source
- description: USB4_2 QMPPHY clock source
- description: USB4_0 PHY DP0 GMUX clock source
- description: USB4_0 PHY DP1 GMUX clock source
- description: USB4_0 PHY PCIE PIPEGMUX clock source
- description: USB4_0 PHY PIPEGMUX clock source
- description: USB4_0 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_1 PHY DP0 GMUX 2 clock source
- description: USB4_1 PHY DP1 GMUX 2 clock source
- description: USB4_1 PHY PCIE PIPEGMUX clock source
- description: USB4_1 PHY PIPEGMUX clock source
- description: USB4_1 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_2 PHY DP0 GMUX 2 clock source
- description: USB4_2 PHY DP1 GMUX 2 clock source
- description: USB4_2 PHY PCIE PIPEGMUX clock source
- description: USB4_2 PHY PIPEGMUX clock source
- description: USB4_2 PHY SYS PCIE PIPEGMUX clock source
- description: USB4_0 PHY RX 0 clock source
- description: USB4_0 PHY RX 1 clock source
- description: USB4_1 PHY RX 0 clock source
- description: USB4_1 PHY RX 1 clock source
- description: USB4_2 PHY RX 0 clock source
- description: USB4_2 PHY RX 1 clock source
- description: USB4_0 PHY PCIE PIPE clock source
- description: USB4_0 PHY max PIPE clock source
- description: USB4_1 PHY PCIE PIPE clock source
- description: USB4_1 PHY max PIPE clock source
- description: USB4_2 PHY PCIE PIPE clock source
- description: USB4_2 PHY max PIPE clock source
power-domains:
description:
@@ -67,7 +94,34 @@ examples:
<&pcie6b_phy>,
<&usb_1_ss0_qmpphy 0>,
<&usb_1_ss1_qmpphy 1>,
<&usb_1_ss2_qmpphy 2>;
<&usb_1_ss2_qmpphy 2>,
<&usb4_0_phy_dp0_gmux_clk>,
<&usb4_0_phy_dp1_gmux_clk>,
<&usb4_0_phy_pcie_pipegmux_clk>,
<&usb4_0_phy_pipegmux_clk>,
<&usb4_0_phy_sys_pcie_pipegmux_clk>,
<&usb4_1_phy_dp0_gmux_2_clk>,
<&usb4_1_phy_dp1_gmux_2_clk>,
<&usb4_1_phy_pcie_pipegmux_clk>,
<&usb4_1_phy_pipegmux_clk>,
<&usb4_1_phy_sys_pcie_pipegmux_clk>,
<&usb4_2_phy_dp0_gmux_2_clk>,
<&usb4_2_phy_dp1_gmux_2_clk>,
<&usb4_2_phy_pcie_pipegmux_clk>,
<&usb4_2_phy_pipegmux_clk>,
<&usb4_2_phy_sys_pcie_pipegmux_clk>,
<&usb4_0_phy_rx_0_clk>,
<&usb4_0_phy_rx_1_clk>,
<&usb4_1_phy_rx_0_clk>,
<&usb4_1_phy_rx_1_clk>,
<&usb4_2_phy_rx_0_clk>,
<&usb4_2_phy_rx_1_clk>,
<&usb4_0_phy_pcie_pipe_clk>,
<&usb4_0_phy_max_pipe_clk>,
<&usb4_1_phy_pcie_pipe_clk>,
<&usb4_1_phy_max_pipe_clk>,
<&usb4_2_phy_pcie_pipe_clk>,
<&usb4_2_phy_max_pipe_clk>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
-1
View File
@@ -99,7 +99,6 @@ properties:
the datasheet.
const: 1
required:
- compatible
- reg
+55
View File
@@ -0,0 +1,55 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rk3506-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RK3506 Clock and Reset Unit (CRU)
maintainers:
- Finley Xiao <[email protected]>
- Heiko Stuebner <[email protected]>
description:
The RK3506 CRU generates the clock and also implements reset for SoC
peripherals.
properties:
compatible:
const: rockchip,rk3506-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
maxItems: 1
clock-names:
const: xin
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
- clocks
- clock-names
additionalProperties: false
examples:
- |
clock-controller@ff9a0000 {
compatible = "rockchip,rk3506-cru";
reg = <0xff9a0000 0x20000>;
#clock-cells = <1>;
#reset-cells = <1>;
clocks = <&xin24m>;
clock-names = "xin";
};
+52
View File
@@ -0,0 +1,52 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/clock/rockchip,rv1126b-cru.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip RV1126B Clock and Reset Unit
maintainers:
- Elaine Zhang <[email protected]>
- Heiko Stuebner <[email protected]>
description:
The rv1126b clock controller generates the clock and also implements a
reset controller for SoC peripherals.
properties:
compatible:
enum:
- rockchip,rv1126b-cru
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
clocks:
maxItems: 1
clock-names:
const: xin24m
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
clock-controller@20000000 {
compatible = "rockchip,rv1126b-cru";
reg = <0x20000000 0xc0000>;
#clock-cells = <1>;
#reset-cells = <1>;
};
@@ -38,6 +38,8 @@ properties:
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
- samsung,exynosautov920-cmu-hsi2
- samsung,exynosautov920-cmu-m2m
- samsung,exynosautov920-cmu-mfc
- samsung,exynosautov920-cmu-misc
- samsung,exynosautov920-cmu-peric0
- samsung,exynosautov920-cmu-peric1
@@ -226,6 +228,46 @@ allOf:
- const: embd
- const: ethernet
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-m2m
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_M2M NOC clock (from CMU_TOP)
- description: CMU_M2M JPEG clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: noc
- const: jpeg
- if:
properties:
compatible:
contains:
const: samsung,exynosautov920-cmu-mfc
then:
properties:
clocks:
items:
- description: External reference clock (38.4 MHz)
- description: CMU_MFC MFC clock (from CMU_TOP)
- description: CMU_MFC WFD clock (from CMU_TOP)
clock-names:
items:
- const: oscclk
- const: mfc
- const: wfd
required:
- compatible
- "#clock-cells"
-26
View File
@@ -114,25 +114,6 @@ allOf:
- reg
properties:
sprd,syscon: false
- if:
properties:
compatible:
contains:
enum:
- sprd,sc9860-agcp-gate
- sprd,sc9860-aon-gate
- sprd,sc9860-apahb-gate
- sprd,sc9860-apapb-gate
- sprd,sc9860-cam-gate
- sprd,sc9860-disp-gate
- sprd,sc9860-pll
- sprd,sc9860-pmu-gate
- sprd,sc9860-vsp-gate
then:
required:
- sprd,syscon
properties:
reg: false
additionalProperties: false
@@ -142,13 +123,6 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
pmu-gate {
compatible = "sprd,sc9860-pmu-gate";
clocks = <&ext_26m>;
#clock-cells = <1>;
sprd,syscon = <&pmu_regs>;
};
clock-controller@20000000 {
compatible = "sprd,sc9860-ap-clk";
reg = <0 0x20000000 0 0x400>;
+1 -1
View File
@@ -8,7 +8,7 @@ title: ST-Ericsson DB8500 (U8500) clocks
maintainers:
- Ulf Hansson <[email protected]>
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: While named "U8500 clocks" these clocks are inside the
DB8500 digital baseband system-on-chip and its siblings such as
-1
View File
@@ -22,7 +22,6 @@ properties:
- xlnx,clocking-wizard-v6.0
- xlnx,versal-clk-wizard
reg:
maxItems: 1
+3
View File
@@ -21,6 +21,9 @@ properties:
dma-coherent: true
iommus:
maxItems: 4
required:
- compatible
- reg
+1 -1
View File
@@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx cryptographic engine
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
@@ -13,6 +13,7 @@ properties:
compatible:
items:
- enum:
- qcom,kaanapali-inline-crypto-engine
- qcom,qcs8300-inline-crypto-engine
- qcom,sa8775p-inline-crypto-engine
- qcom,sc7180-inline-crypto-engine
+1
View File
@@ -20,6 +20,7 @@ properties:
- qcom,ipq5332-trng
- qcom,ipq5424-trng
- qcom,ipq9574-trng
- qcom,kaanapali-trng
- qcom,qcs615-trng
- qcom,qcs8300-trng
- qcom,sa8255p-trng
+1
View File
@@ -45,6 +45,7 @@ properties:
- items:
- enum:
- qcom,kaanapali-qce
- qcom,qcs615-qce
- qcom,qcs8300-qce
- qcom,sa8775p-qce
+8 -5
View File
@@ -19,11 +19,14 @@ description: |
properties:
compatible:
enum:
- nvidia,tegra30-actmon
- nvidia,tegra114-actmon
- nvidia,tegra124-actmon
- nvidia,tegra210-actmon
oneOf:
- enum:
- nvidia,tegra30-actmon
- nvidia,tegra114-actmon
- nvidia,tegra124-actmon
- items:
- const: nvidia,tegra210-actmon
- const: nvidia,tegra124-actmon
reg:
maxItems: 1
@@ -121,5 +121,4 @@ examples:
};
};
...
@@ -121,5 +121,4 @@ examples:
};
};
...
@@ -142,7 +142,6 @@ then:
reset-names:
minItems: 2
additionalProperties: false
examples:
-1
View File
@@ -25,7 +25,6 @@ description: |
M |-------|______|----|____________| |________________| | |
___|__________________________________________________________|_______________|
VIU: Video Input Unit
---------------------
+62 -14
View File
@@ -56,22 +56,12 @@ properties:
- const: cec
interrupts:
items:
- description: CEC TX interrupt
- description: CEC RX interrupt
- description: CEC stuck at low interrupt
- description: Wake-up interrupt
- description: Hotplug connected interrupt
- description: Hotplug removed interrupt
minItems: 5
maxItems: 6
interrupt-names:
items:
- const: cec-tx
- const: cec-rx
- const: cec-low
- const: wakeup
- const: hpd-connected
- const: hpd-removed
minItems: 5
maxItems: 6
ddc:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -112,6 +102,61 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm2711-hdmi0
- brcm,bcm2711-hdmi1
then:
properties:
interrupts:
items:
- description: CEC TX interrupt
- description: CEC RX interrupt
- description: CEC stuck at low interrupt
- description: Wake-up interrupt
- description: Hotplug connected interrupt
- description: Hotplug removed interrupt
interrupt-names:
items:
- const: cec-tx
- const: cec-rx
- const: cec-low
- const: wakeup
- const: hpd-connected
- const: hpd-removed
- if:
properties:
compatible:
contains:
enum:
- brcm,bcm2712-hdmi0
- brcm,bcm2712-hdmi1
then:
properties:
interrupts:
items:
- description: CEC TX interrupt
- description: CEC RX interrupt
- description: CEC stuck at low interrupt
- description: Hotplug connected interrupt
- description: Hotplug removed interrupt
interrupts-names:
items:
- const: cec-tx
- const: cec-rx
- const: cec-low
- const: hpd-connected
- const: hpd-removed
required:
- interrupts
- interrupt-names
examples:
- |
hdmi0: hdmi@7ef00700 {
@@ -136,6 +181,9 @@ examples:
"hd";
clocks = <&firmware_clocks 13>, <&firmware_clocks 14>, <&dvp 1>, <&clk_27MHz>;
clock-names = "hdmi", "bvb", "audio", "cec";
interrupts = <0>, <1>, <2>, <3>, <4>, <5>;
interrupt-names = "cec-tx", "cec-rx", "cec-low", "wakeup",
"hpd-connected", "hpd-removed";
resets = <&dvp 0>;
ddc = <&ddc0>;
};
+73 -13
View File
@@ -20,11 +20,20 @@ properties:
maxItems: 1
interrupts:
maxItems: 1
minItems: 1
maxItems: 3
interrupt-names:
minItems: 1
maxItems: 3
clocks:
maxItems: 1
description: Core Clock
minItems: 1
maxItems: 2
clock-names:
minItems: 1
maxItems: 2
required:
- compatible
@@ -33,17 +42,68 @@ required:
additionalProperties: false
if:
properties:
compatible:
contains:
enum:
- brcm,bcm2711-hvs
- brcm,bcm2712-hvs
allOf:
- if:
properties:
compatible:
contains:
const: brcm,bcm2711-hvs
then:
required:
- clocks
then:
properties:
clocks:
items:
- description: Core Clock
interrupts:
maxItems: 1
clock-names: false
interrupt-names: false
required:
- clocks
- if:
properties:
compatible:
contains:
const: brcm,bcm2712-hvs
then:
properties:
clocks:
minItems: 2
maxItems: 2
clock-names:
items:
- const: core
- const: disp
interrupts:
items:
- description: Channel 0 End of frame
- description: Channel 1 End of frame
- description: Channel 2 End of frame
interrupt-names:
items:
- const: ch0-eof
- const: ch1-eof
- const: ch2-eof
required:
- clocks
- clock-names
- interrupt-names
- if:
properties:
compatible:
contains:
const: brcm,bcm2835-hvs
then:
properties:
interrupts:
maxItems: 1
clock-names: false
interrupt-names: false
examples:
- |
-1
View File
@@ -156,7 +156,6 @@ else:
adi,input-style: false
adi,input-justification: false
required:
- compatible
- reg
@@ -49,6 +49,10 @@ properties:
$ref: /schemas/graph.yaml#/properties/port
description: HDMI output port
port@2:
$ref: /schemas/graph.yaml#/properties/port
description: Parallel audio input port
required:
- port@0
- port@1
@@ -98,5 +102,13 @@ examples:
remote-endpoint = <&hdmi0_con>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&pai_to_hdmi_tx>;
};
};
};
};
+1
View File
@@ -19,6 +19,7 @@ properties:
compatible:
enum:
- ite,it66121
- ite,it66122
- ite,it6610
reg:
-1
View File
@@ -131,7 +131,6 @@ required:
additionalProperties: false
examples:
- |
lvds-encoder {
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
@@ -14,6 +14,9 @@ description: |
R-Car Gen4 SoCs. The encoder can operate in either DSI or CSI-2 mode, with up
to four data lanes.
allOf:
- $ref: /schemas/display/dsi-controller.yaml#
properties:
compatible:
enum:
@@ -80,14 +83,14 @@ required:
- resets
- ports
additionalProperties: false
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/r8a779a0-cpg-mssr.h>
#include <dt-bindings/power/r8a779a0-sysc.h>
dsi0: dsi-encoder@fed80000 {
dsi@fed80000 {
compatible = "renesas,r8a779a0-dsi-csi2-tx";
reg = <0xfed80000 0x10000>;
power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>;
@@ -117,4 +120,51 @@ examples:
};
};
};
- |
#include <dt-bindings/clock/r8a779g0-cpg-mssr.h>
#include <dt-bindings/power/r8a779g0-sysc.h>
dsi@fed80000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,r8a779g0-dsi-csi2-tx";
reg = <0xfed80000 0x10000>;
clocks = <&cpg CPG_MOD 415>,
<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
clock-names = "fck", "dsi", "pll";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 415>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
};
port@1 {
reg = <1>;
dsi0port1_out: endpoint {
remote-endpoint = <&panel_in>;
data-lanes = <1 2>;
};
};
};
panel@0 {
reg = <0>;
compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c";
power-supply = <&vcc_lcd_reg>;
port {
panel_in: endpoint {
remote-endpoint = <&dsi0port1_out>;
};
};
};
};
...
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Silicon Image SiI8620 HDMI/MHL bridge
maintainers:
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
- Krzysztof Kozlowski <krzk@kernel.org>
properties:
compatible:
@@ -27,7 +27,9 @@ properties:
- const: adi,adv7123
- enum:
- adi,adv7123
- asl-tek,cs5263
- dumb-vga-dac
- parade,ps185hdm
- radxa,ra620
- realtek,rtd2171
- ti,opa362
@@ -123,7 +123,6 @@ properties:
- required:
- port@1
required:
- compatible
- reg
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Common Properties for DSI Display Panels
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
description: |
This document defines device tree properties common to DSI, Display
+1 -1
View File
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Faraday TV Encoder TVE200
maintainers:
- Linus Walleij <linus.walleij@linaro.org>
- Linus Walleij <linusw@kernel.org>
properties:
compatible:
-1
View File
@@ -54,7 +54,6 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
display@0{
compatible = "waveshare,rpi-lcd-35", "ilitek,ili9486";
reg = <0>;
@@ -0,0 +1,69 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/imx/fsl,imx8mp-hdmi-pai.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX8MP HDMI Parallel Audio Interface
maintainers:
- Shengjiu Wang <[email protected]>
description:
The HDMI TX Parallel Audio Interface (HTX_PAI) is a bridge between the
Audio Subsystem to the HDMI TX Controller.
properties:
compatible:
const: fsl,imx8mp-hdmi-pai
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
clock-names:
const: apb
power-domains:
maxItems: 1
port:
$ref: /schemas/graph.yaml#/properties/port
description: Output to the HDMI TX controller.
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
#include <dt-bindings/power/imx8mp-power.h>
audio-bridge@32fc4800 {
compatible = "fsl,imx8mp-hdmi-pai";
reg = <0x32fc4800 0x800>;
interrupt-parent = <&irqsteer_hdmi>;
interrupts = <14>;
clocks = <&clk IMX8MP_CLK_HDMI_APB>;
clock-names = "apb";
power-domains = <&hdmi_blk_ctrl IMX8MP_HDMIBLK_PD_PAI>;
port {
pai_to_hdmi_tx: endpoint {
remote-endpoint = <&hdmi_tx_from_pai>;
};
};
};
+1 -1
View File
@@ -11,7 +11,7 @@ maintainers:
- Jitao shi <[email protected]>
description: |
MediaTek DP and eDP are different hardwares and there are some features
MediaTek DP and eDP are different hardware and there are some features
which are not supported for eDP. For example, audio is not supported for
eDP. Therefore, we need to use two different compatibles to describe them.
In addition, We just need to enable the power domain of DP, so the clock
+16 -1
View File
@@ -18,6 +18,7 @@ properties:
compatible:
oneOf:
- enum:
- qcom,glymur-dp
- qcom,sa8775p-dp
- qcom,sc7180-dp
- qcom,sc7280-dp
@@ -31,6 +32,11 @@ properties:
- qcom,sm8650-dp
- qcom,x1e80100-dp
- items:
- enum:
- qcom,qcs8300-dp
- const: qcom,sa8775p-dp
- items:
- enum:
- qcom,sm6350-dp
@@ -53,6 +59,12 @@ properties:
- qcom,sm8550-dp
- const: qcom,sm8350-dp
- items:
- enum:
- qcom,sm6150-dp
- const: qcom,sm8150-dp
- const: qcom,sm8350-dp
- items:
- enum:
- qcom,sm8750-dp
@@ -195,9 +207,11 @@ allOf:
compatible:
contains:
enum:
- qcom,glymur-dp
- qcom,sa8775p-dp
- qcom,x1e80100-dp
then:
$ref: /schemas/sound/dai-common.yaml#
oneOf:
- required:
- aux-bus
@@ -239,6 +253,7 @@ allOf:
enum:
# these platforms support 2 streams MST on some interfaces,
# others are SST only
- qcom,glymur-dp
- qcom,sc8280xp-dp
- qcom,x1e80100-dp
then:
@@ -295,7 +310,7 @@ allOf:
minItems: 6
maxItems: 8
additionalProperties: false
unevaluatedProperties: false
examples:
- |
+59 -1
View File
@@ -21,7 +21,7 @@ properties:
compatible:
oneOf:
- items:
- pattern: '^qcom,adreno-gmu-[67][0-9][0-9]\.[0-9]$'
- pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
- const: qcom,adreno-gmu
- items:
- pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
@@ -299,6 +299,64 @@ allOf:
required:
- qcom,qmp
- if:
properties:
compatible:
contains:
const: qcom,adreno-gmu-840.1
then:
properties:
reg:
items:
- description: Core GMU registers
reg-names:
items:
- const: gmu
clocks:
items:
- description: GPU AHB clock
- description: GMU clock
- description: GPU CX clock
- description: GPU MEMNOC clock
- description: GMU HUB clock
clock-names:
items:
- const: ahb
- const: gmu
- const: cxo
- const: memnoc
- const: hub
- if:
properties:
compatible:
contains:
const: qcom,adreno-gmu-x285.1
then:
properties:
reg:
items:
- description: Core GMU registers
reg-names:
items:
- const: gmu
clocks:
items:
- description: GPU AHB clock
- description: GMU clock
- description: GPU CX clock
- description: GPU MEMNOC clock
- description: GMU HUB clock
- description: GMU RSCC HUB clock
clock-names:
items:
- const: ahb
- const: gmu
- const: cxo
- const: memnoc
- const: hub
- const: rscc
- if:
properties:
compatible:
-1
View File
@@ -133,7 +133,6 @@ properties:
For GMU attached devices a phandle to the GMU device that will
control the power for the GPU.
required:
- compatible
- reg
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