misc: Avoid use of Unicode closing single quote

The Unicode closing single quotation mark is classified as a homoglyph
and can trip automated code quality checks in downstream CI pipelines or
cause code review UIs to refuse to display a file.  If used as an
apostrophe, use the ASCII single quote instead.  If used as a closing
single quote, replace with double quotes or no quotes at all.

Sponsored by:	Klara, Inc.
Sponsored by:	NetApp, Inc.
Reviewed by:	ziaee, obiwac, olce
Differential Revision:	https://reviews.freebsd.org/D59911

UPDATING

@@ -756,7 +756,7 @@ NOTE TO PEOPLE WHO THINK THAT FreeBSD 16.x IS SLOW:
 	custom kernel configurations without any additional change.
 
 20230922:
-	A new loader tunable net.pf.default_to_drop allows pf(4)’s default
+	A new loader tunable net.pf.default_to_drop allows pf(4)'s default
 	behaviour to be changed from pass to drop. Previously this required
 	recompiling the kernel with the option PF_DEFAULT_TO_DROP.
 

sbin/nvmecontrol/nvmecontrol.8

@@ -469,10 +469,10 @@ Change Persist Through Power Loss State:
 .It Dv 0
 No change to PTPL state
 .It Dv 2
-Set PTPL state to ‘0’.
+Set PTPL state to 0.
 Reservations are released and registrants are cleared on a power on.
 .It Dv 3
-Set PTPL state to ‘1’.
+Set PTPL state to 1.
 Reservations and registrants persist across a power loss.
 .El
 .El

sys/arm/annapurna/alpine/alpine_pci_msix.c

@@ -254,7 +254,7 @@ al_msix_map_msi(device_t dev, device_t child, struct intr_irqsrc *isrc,
 	 *           Same value as the MSIx Translation Base  Address Register
 	 * [19]    - WFE_EXIT
 	 *           Once set by MSIx message, an EVENTI is signal to the CPUs
-	 *           cluster specified by ‘Local GIC Target List’
+	 *           cluster specified by “Local GIC Target List”
 	 * [18:17] - Target GIC ID
 	 *           Specifies which IO-GIC (external shared GIC) is targeted
 	 *           0: Local GIC, as specified by the Local GIC Target List

sys/cddl/dev/dtrace/x86/dis_tables.c

@@ -3121,7 +3121,7 @@ dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W,
 /*
  * The following three functions adjust the register selection based on any
  * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software
- * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and
+ * Developer's Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and
  * section 2.6.2 Table 2-31.
  */
 static void

sys/dev/atkbdc/psm.c

@@ -3680,7 +3680,7 @@ proc_synaptics_mux(struct psm_softc *sc, packetbuf_t *pb)
 	 * While in hidden multiplexing mode KBC does some editing of the
 	 * packet stream. It remembers the button bits from the last packet
 	 * received from each device, and replaces the button bits of every
-	 * packet with the logical OR of all devices’ most recent button bits.
+	 * packet with the logical OR of all devices' most recent button bits.
 	 * This button crosstalk should be filtered out as Synaptics and
 	 * generic mouse encode middle button presses in a different way.
 	 */

sys/dev/dpaa2/dpaa2_io.c

@@ -33,7 +33,7 @@
  * optional notification capabilities.
  *
  * Software portals are used by the driver to communicate with the QBMan. The
- * DPIO object’s main purpose is to enable the driver to perform I/O – enqueue
+ * DPIO object's main purpose is to enable the driver to perform I/O – enqueue
  * and dequeue operations, as well as buffer release and acquire operations –
  * using QBMan.
  */

sys/dev/hid/hidmap.c

@@ -220,7 +220,7 @@ hidmap_intr(void *context, void *buf, hid_size_t len)
 		 * 5.8. If Logical Minimum and Logical Maximum are both
 		 * positive values then the contents of a field can be assumed
 		 * to be an unsigned value. Otherwise, all integer values are
-		 * signed values represented in 2’s complement format.
+		 * signed values represented in two's complement format.
 		 */
 		data = hi->lmin < 0 || hi->lmax < 0
 		    ? hid_get_data(buf, len, &hi->loc)

sys/dev/oce/oce_hw.h

@@ -1719,7 +1719,7 @@ enum CQFW_CONFIG_NUMBER {
 /**
  * @brief Function Capabilites
  * This field contains the flags indicating the capabilities of
- * the SLI Host’s PCI function.
+ * the SLI Host's PCI function.
  */
 enum CQFW_FUNCTION_CAPABILITIES {
 	FNC_UNCLASSIFIED_STATS = 0x1,
@@ -1748,7 +1748,7 @@ enum CQFW_ULP_MODES_SUPPORTED {
 
 /**
  * @brief Function Modes Supported
- * Valid function modes (or protocol-types) supported on the SLI-Host’s
+ * Valid function modes (or protocol-types) supported on the SLI-Host's
  * PCIe function.  This field is a logical OR of the following values:
  */
 enum CQFW_FUNCTION_MODES_SUPPORTED {

sys/dev/smartpqi/smartpqi_init.c

@@ -251,7 +251,7 @@ pqisrc_decide_opq_config(pqisrc_softstate_t *softs)
 		softs->share_opq_and_eventq = false;
 	}
 	/* If the available interrupt count is more than one,
-	we don’t need to share the interrupt for IO and event queue */
+	we don't need to share the interrupt for IO and event queue */
 	if (softs->intr_count > 1)
 		softs->share_opq_and_eventq = false;
 

sys/dev/virtio/mmio/virtio_mmio.c

@@ -692,7 +692,7 @@ vtmmio_read_dev_config(device_t dev, bus_size_t offset,
 	 *   format for multi-byte fields.
 	 *
 	 *   2.4.3: Note that for legacy interfaces, device configuration space
-	 *   is generally the guest’s native endian, rather than PCI’s
+	 *   is generally the guest's native endian, rather than PCI's
 	 *   little-endian. The correct endian-ness is documented for each
 	 *   device.
 	 */

sys/net/sff8436.h

@@ -187,7 +187,7 @@ enum {
 	SFF_8436_OPTIONS_END	= 195,
 	SFF_8436_SN_START 	= 196,	/* Vendor SN, riwght padded with 0x20 */
 	SFF_8436_SN_END 	= 211,
-	SFF_8436_DATE_START	= 212,	/* Vendor’s manufacturing date code
+	SFF_8436_DATE_START	= 212,	/* Vendor's manufacturing date code
 					* (see Table 40) */
 	SFF_8436_DATE_END	= 219,
 	SFF_8436_DIAG_TYPE	= 220,	/* Diagnostic Monitoring Type

sys/net/sff8472.h

@@ -130,7 +130,7 @@ enum {
 				    * 25.0Gb/s) */
 	SFF_8472_SN_START 	= 68, /* Vendor SN [Address A0h, Bytes 68-83] */
 	SFF_8472_SN_END 	= 83,
-	SFF_8472_DATE_START	= 84, /* Date code Vendor’s manufacturing
+	SFF_8472_DATE_START	= 84, /* Date code Vendor's manufacturing
 				    * date code (see Table 3.8) */
 	SFF_8472_DATE_END	= 91,
 	SFF_8472_DIAG_TYPE	= 92, /* Diagnostic Monitoring Type
@@ -244,7 +244,7 @@ enum {
 				    * set to 1 for “internally
 				    * calibrated” devices. */
 	SFF_8472_TX_I_OFFSET	= 78, /* Tx_I(Offset) Fixed decimal
-				    * (signed two’s complement)
+				    * (signed two's complement)
 				    * calibration data, laser bias
 				    * current. Bit 7 of byte 78 is
 				    * MSB, bit 0 of byte 79 is
@@ -260,7 +260,7 @@ enum {
 				    * for “internally calibrated”
 				    * devices. */
 	SFF_8472_TX_POWER_OFFSET	= 82, /* Tx_PWR(Offset) Fixed decimal
-					    * (signed two’s complement)
+					    * (signed two's complement)
 					    * calibration data, transmitter
 					    * coupled output power. Bit 7 of
 					    * byte 82 is MSB, bit 0 of byte 83
@@ -275,7 +275,7 @@ enum {
 				    * be set to 1 for “internally
 				    * calibrated” devices. */
 	SFF_8472_T_OFFSET	= 86, /* T (Offset) Fixed decimal (signed
-				    * two’s complement) calibration
+				    * two's complement) calibration
 				    * data, internal module
 				    * temperature. Bit 7 of byte 86 is
 				    * MSB, bit 0 of byte 87 is LSB.
@@ -291,7 +291,7 @@ enum {
 				    * for “internally calibrated”
 				    * devices. */
 	SFF_8472_V_OFFSET	= 90, /* V (Offset) Fixed decimal (signed
-				    * two’s complement) calibration
+				    * two's complement) calibration
 				    * data, internal module supply
 				    * voltage. Bit 7 of byte 90 is
 				    * MSB. Bit 0 of byte 91 is
@@ -323,7 +323,7 @@ enum {
 
 /*
  * Select Read/write bit that allows software disable of
- * laser. Writing ‘1’ disables laser. See Table 3.11 for
+ * laser. Writing 1 disables laser. See Table 3.11 for
  * enable/disable timing requirements. This bit is “OR”d with the hard
  * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default
  * enabled unless pulled low by hardware. If Soft TX Disable is not
@@ -348,7 +348,7 @@ enum {
      
 /*
  * Read/write bit that allows software rate select control. Writing
- * ‘1’ selects full bandwidth operation. This bit is “OR’d with the
+ * 1 selects full bandwidth operation. This bit is “OR”d with the
  * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for
  * timing requirements. Default at power up is logic zero/low. If Soft
  * Rate Select is not implemented, the transceiver ignores the value

sys/x86/x86/identcpu.c

@@ -1554,7 +1554,7 @@ fix_cpuid(void)
 	 * Re-enable AMD Topology Extension that could be disabled by BIOS
 	 * on some notebook processors.  Without the extension it's really
 	 * hard to determine the correct CPU cache topology.
-	 * See BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 15h
+	 * See BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h
 	 * Models 60h-6Fh Processors, Publication # 50742.
 	 */
 	if (vm_guest == VM_GUEST_NO && cpu_vendor_id == CPU_VENDOR_AMD &&

sys/x86/x86/mp_x86.c

@@ -360,7 +360,7 @@ topo_probe_amd(void)
  * using CPUID Leaf 1 and Leaf 4, if supported.
  * See:
  *  - Intel 64 Architecture Processor Topology Enumeration
- *  - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
+ *  - Intel 64 and IA-32 Architectures Software Developer's Manual,
  *    Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
  *    FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
  */
@@ -394,7 +394,7 @@ topo_probe_intel_0x4(void)
  * using CPUID Leaf 1Fh or 0Bh, if supported.
  * See:
  *  - Intel 64 Architecture Processor Topology Enumeration
- *  - Intel 64 and IA-32 ArchitecturesSoftware Developer’s Manual,
+ *  - Intel 64 and IA-32 Architectures Software Developer's Manual,
  *    Volume 3A: System Programming Guide, PROGRAMMING CONSIDERATIONS
  *    FOR HARDWARE MULTI-THREADING CAPABLE PROCESSORS
  */
@@ -451,7 +451,7 @@ topo_probe_intel_0xb(void)
  * Determine topology of caches for Intel CPUs.
  * See:
  *  - Intel 64 Architecture Processor Topology Enumeration
- *  - Intel 64 and IA-32 Architectures Software Developer’s Manual
+ *  - Intel 64 and IA-32 Architectures Software Developer's Manual
  *    Volume 2A: Instruction Set Reference, A-M,
  *    CPUID instruction
  */

usr.sbin/bhyve/bhyve.8

@@ -1436,7 +1436,7 @@ bhyve -c 4 -s 0,hostbridge -s 1,lpc -s 2,virtio-blk,/my/image \\
 .Pp
 .Rs
 .%A Intel
-.%B 64 and IA-32 Architectures Software Developer’s Manual
+.%B 64 and IA-32 Architectures Software Developer's Manual
 .%V Volume 3
 .Re
 .Sh HISTORY

usr.sbin/moused/moused/moused.conf.5

@@ -55,7 +55,7 @@ Section names are free-form and may contain spaces.
 .Bl -tag -width indent
 .It MatchName, MatchUniq
 Match on the NAME or UNIQ udev property on this device. These
-properties are typically derived from the device’s kernel name or uniq.
+properties are typically derived from the device's kernel name or uniq.
 These matches use
 .Fn fnmatch
 globs.