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arm64: Fix the MPIDR_EL1 field names

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Use the field names from the Arm Documentation for the MPIDR_EL1
register. These will later be generated from a BSD Licensed JSON file
so to reduce the diff for that rename now.

Reviewed by:	kajetan.puchalski_arm.com
Sponsored by:   Arm Ltd
Differential Revision:	https://reviews.freebsd.org/D59176
This commit is contained in:
Andrew Turner committed 2026-10-09 12:55:14 +01:00
1 parent e8997a4e44
commit 6bf6fe1d70
3 files changed
+19 -19
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sys/arm64/include/armreg.h
+12 -12
View File
@@ -2141,22 +2141,22 @@
#define MPIDR_EL1_CRn 0
#define MPIDR_EL1_CRm 0
#define MPIDR_EL1_op2 5
#define MPIDR_AFF0_SHIFT 0
#define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT)
#define MPIDR_AFF0_VAL(x) ((x) & MPIDR_AFF0_MASK)
#define MPIDR_AFF1_SHIFT 8
#define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT)
#define MPIDR_AFF1_VAL(x) ((x) & MPIDR_AFF1_MASK)
#define MPIDR_AFF2_SHIFT 16
#define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT)
#define MPIDR_AFF2_VAL(x) ((x) & MPIDR_AFF2_MASK)
#define MPIDR_Aff0_SHIFT 0
#define MPIDR_Aff0_MASK (UL(0xff) << MPIDR_Aff0_SHIFT)
#define MPIDR_Aff0_VAL(x) ((x) & MPIDR_Aff0_MASK)
#define MPIDR_Aff1_SHIFT 8
#define MPIDR_Aff1_MASK (UL(0xff) << MPIDR_Aff1_SHIFT)
#define MPIDR_Aff1_VAL(x) ((x) & MPIDR_Aff1_MASK)
#define MPIDR_Aff2_SHIFT 16
#define MPIDR_Aff2_MASK (UL(0xff) << MPIDR_Aff2_SHIFT)
#define MPIDR_Aff2_VAL(x) ((x) & MPIDR_Aff2_MASK)
#define MPIDR_MT_SHIFT 24
#define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT)
#define MPIDR_U_SHIFT 30
#define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT)
#define MPIDR_AFF3_SHIFT 32
#define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT)
#define MPIDR_AFF3_VAL(x) ((x) & MPIDR_AFF3_MASK)
#define MPIDR_Aff3_SHIFT 32
#define MPIDR_Aff3_MASK (UL(0xff) << MPIDR_Aff3_SHIFT)
#define MPIDR_Aff3_VAL(x) ((x) & MPIDR_Aff3_MASK)
/* MVFR0_EL1 */
#define MVFR0_EL1_ISS ISS_MSR_REG(MVFR0_EL1)
sys/arm64/vmm/io/vgic_v3.c
+3 -3
View File
@@ -1633,8 +1633,8 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg)
aff1 = ICC_SGI1R_Aff1_VAL(rval) >> ICC_SGI1R_Aff1_SHIFT;
aff2 = ICC_SGI1R_Aff2_VAL(rval) >> ICC_SGI1R_Aff2_SHIFT;
aff3 = ICC_SGI1R_Aff3_VAL(rval) >> ICC_SGI1R_Aff3_SHIFT;
mpidr = aff3 << MPIDR_AFF3_SHIFT |
aff2 << MPIDR_AFF2_SHIFT | aff1 << MPIDR_AFF1_SHIFT;
mpidr = aff3 << MPIDR_Aff3_SHIFT |
aff2 << MPIDR_Aff2_SHIFT | aff1 << MPIDR_Aff1_SHIFT;
cpus = ICC_SGI1R_TargetList_VAL(rval) >>
ICC_SGI1R_TargetList_SHIFT;
@@ -1642,7 +1642,7 @@ vgic_v3_icc_sgi1r_write(struct vcpu *vcpu, uint64_t rval, void *arg)
while (cpus > 0) {
if (cpus & 1) {
target_vcpuid = mpidr_to_vcpu(hyp,
mpidr | (cpu_off << MPIDR_AFF0_SHIFT));
mpidr | (cpu_off << MPIDR_Aff0_SHIFT));
if (target_vcpuid >= 0 &&
CPU_ISSET(target_vcpuid, &active_cpus)) {
INJECT_IRQ(hyp, target_vcpuid, irqid,
sys/arm64/vmm/vmm_reset.c
+4 -4
View File
@@ -120,10 +120,10 @@ reset_vm_el2_regs(void *vcpu)
* Generate the guest MPIDR value. We only support 16 CPUs at affinity
* level 0 to simplify the vgicv3 driver (see writing sgi1r_el1).
*/
cpu_aff = (vcpuid & 0xf) << MPIDR_AFF0_SHIFT |
((vcpuid >> 4) & 0xff) << MPIDR_AFF1_SHIFT |
((vcpuid >> 12) & 0xff) << MPIDR_AFF2_SHIFT |
((vcpuid >> 20) & 0xff) << MPIDR_AFF3_SHIFT;
cpu_aff = (vcpuid & 0xf) << MPIDR_Aff0_SHIFT |
((vcpuid >> 4) & 0xff) << MPIDR_Aff1_SHIFT |
((vcpuid >> 12) & 0xff) << MPIDR_Aff2_SHIFT |
((vcpuid >> 20) & 0xff) << MPIDR_Aff3_SHIFT;
*hypctx_sys_reg(el2ctx, HOST_VMPIDR_EL2) |= cpu_aff;
/* Use the same CPU identification information as the host */