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Anurag Kumar Vulisha
cea0f76a48
Add DT bindings for the Xilinx ZynqMP PHY. ZynqMP SoCs have a High Speed Processing System Gigabit Transceiver which provides PHY capabilities to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <[email protected]> Signed-off-by: Laurent Pinchart <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
24 lines
511 B
C
24 lines
511 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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*
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* This header provides constants for the phy framework
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*
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* Copyright (C) 2014 STMicroelectronics
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* Author: Gabriel Fernandez <[email protected]>
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*/
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#ifndef _DT_BINDINGS_PHY
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#define _DT_BINDINGS_PHY
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#define PHY_NONE 0
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#define PHY_TYPE_SATA 1
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#define PHY_TYPE_PCIE 2
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#define PHY_TYPE_USB2 3
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#define PHY_TYPE_USB3 4
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#define PHY_TYPE_UFS 5
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#define PHY_TYPE_DP 6
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#define PHY_TYPE_XPCS 7
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#define PHY_TYPE_SGMII 8
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#endif /* _DT_BINDINGS_PHY */
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