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Merge tag 'soc-fixes-7.3-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Browse Source 
Pull SoC fixes from Arnd Bergmann:
 "A small number of last minute bug fixes came up since LPC.
  Most of these are for devicetree files:

   - Tegra264 needs fan descriptions to keep the system from overheating

   - A cleanup on TI DRA7 caused a regression on PCI support and needs a
     fixup

   - The beaglev-fire board can no longer probe the mcp3564 sensor after
     a an inconsistent update in 7.1

   - A few fixes address compile time dtc warnings on tegra

  The other three patches are all addressing minor problems
  in tegra drivers and the sama5 defconfig"

* tag 'soc-fixes-7.3-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: configs: sama5: enable current Microchip KSZ DSA symbols
  soc/tegra: pmc: Fix uninitialised clock rate
  riscv: dts: microchip: beaglev-fire: remove double definition of gpio interrupts
  ARM: dts: ti/omap: dra7: fix PCIe PHY clock divider definition
  soc/tegra: fuse: Add missing newline to APBMISC error message
  arm64: tegra: Add PCIe root ports on Tegra264
  arm64: tegra: Reorder reg and reg-names to match bindings
  arm64: tegra: Add PWM fan on Jetson AGX Thor DevKit
  arm64: tegra: Add PWM controllers on Tegra264
This commit is contained in:
Linus Torvalds committed 2026-10-15 15:10:26 -07:00
2 parents 62f482ff73 59f522f5a0
commit 2f2f7eeef8
7 files changed
+174 -46
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arch/arm/boot/dts/ti/omap/dra7xx-clocks.dtsi
+1 -1
View File
@@ -1376,8 +1376,8 @@
clocks = <&apll_pcie_ck>;
#clock-cells = <0>;
reg = <0x021c>;
ti,dividers = <2>, <1>;
ti,bit-shift = <8>;
ti,max-div = <2>;
};
apll_pcie_clkvcoldo: clock-apll-pcie-clkvcoldo {
arch/arm/configs/sama5_defconfig
+2 -2
View File
@@ -69,8 +69,8 @@ CONFIG_BLK_DEV_SD=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_SCSI_LOWLEVEL is not set
CONFIG_NETDEVICES=y
CONFIG_NET_DSA_MICROCHIP_KSZ9477=m
CONFIG_NET_DSA_MICROCHIP_KSZ9477_SPI=m
CONFIG_NET_DSA_MICROCHIP_KSZ_COMMON=m
CONFIG_NET_DSA_MICROCHIP_KSZ_SPI=m
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_MACB=y
# CONFIG_NET_VENDOR_CIRRUS is not set
arch/arm64/boot/dts/nvidia/tegra264-p4071-0000+p3834.dtsi
+13
View File
@@ -9,4 +9,17 @@
chosen {
stdout-path = "serial0:115200n8";
};
bus@0 {
pwm@c6a0000 {
status = "okay";
};
};
fan: pwm-fan {
compatible = "pwm-fan";
cooling-levels = <77 102 140 192 255>;
pwms = <&pwm4 0 40000>;
#cooling-cells = <2>;
};
};
arch/arm64/boot/dts/nvidia/tegra264.dtsi
+156 -24
View File
@@ -3356,6 +3356,18 @@
status = "disabled";
};
pwm4: pwm@c6a0000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc6a0000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM4>;
resets = <&bpmp TEGRA264_RESET_PWM4>;
reset-names = "pwm";
#pwm-cells = <2>;
};
pinmux_aon: pinmux@c7a2000 {
compatible = "nvidia,tegra264-pinmux-aon";
reg = <0x0 0x0c7a2000 0x0 0x2000>;
@@ -3537,11 +3549,11 @@
pci@c000000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xd0 0xb0000000 0x0 0x10000000>,
<0x00 0x0c000000 0x0 0x00004000>,
reg = <0x00 0x0c000000 0x0 0x00004000>,
<0x00 0x0c004000 0x0 0x00001000>,
<0x00 0x0c005000 0x0 0x00001000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri";
<0x00 0x0c005000 0x0 0x00001000>,
<0xd0 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -3565,6 +3577,16 @@
nvidia,bpmp = <&bpmp 0>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pinmux_main: pinmux@c281000 {
@@ -3661,6 +3683,66 @@
status = "disabled";
};
pwm2: pwm@c5e0000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc5e0000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM2>;
resets = <&bpmp TEGRA264_RESET_PWM2>;
reset-names = "pwm";
#pwm-cells = <2>;
};
pwm3: pwm@c5f0000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc5f0000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM3>;
resets = <&bpmp TEGRA264_RESET_PWM3>;
reset-names = "pwm";
#pwm-cells = <2>;
};
pwm5: pwm@c600000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc600000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM5>;
resets = <&bpmp TEGRA264_RESET_PWM5>;
reset-names = "pwm";
#pwm-cells = <2>;
};
pwm9: pwm@c610000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc610000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM9>;
resets = <&bpmp TEGRA264_RESET_PWM9>;
reset-names = "pwm";
#pwm-cells = <2>;
};
pwm10: pwm@c620000 {
compatible = "nvidia,tegra264-pwm";
reg = <0x0 0xc620000 0x0 0x10000>;
status = "disabled";
clocks = <&bpmp TEGRA264_CLK_PWM10>;
resets = <&bpmp TEGRA264_RESET_PWM10>;
reset-names = "pwm";
#pwm-cells = <2>;
};
i2c0: i2c@c630000 {
compatible = "nvidia,tegra264-i2c";
reg = <0x00 0x0c630000 0x0 0x10000>;
@@ -3990,12 +4072,12 @@
pci@8400000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xa8 0xb0000000 0x0 0x10000000>,
<0x00 0x08400000 0x0 0x00004000>,
reg = <0x00 0x08400000 0x0 0x00004000>,
<0x00 0x08404000 0x0 0x00001000>,
<0x00 0x08405000 0x0 0x00001000>,
<0x00 0x08410000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08410000 0x0 0x00010000>,
<0xa8 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -4018,16 +4100,26 @@
nvidia,bpmp = <&bpmp 1>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pci@8420000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xb0 0xb0000000 0x0 0x10000000>,
<0x00 0x08420000 0x0 0x00004000>,
reg = <0x00 0x08420000 0x0 0x00004000>,
<0x00 0x08424000 0x0 0x00001000>,
<0x00 0x08425000 0x0 0x00001000>,
<0x00 0x08430000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08430000 0x0 0x00010000>,
<0xb0 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -4050,16 +4142,26 @@
nvidia,bpmp = <&bpmp 2>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pci@8440000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xb8 0xb0000000 0x0 0x10000000>,
<0x00 0x08440000 0x0 0x00004000>,
reg = <0x00 0x08440000 0x0 0x00004000>,
<0x00 0x08444000 0x0 0x00001000>,
<0x00 0x08445000 0x0 0x00001000>,
<0x00 0x08450000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08450000 0x0 0x00010000>,
<0xb8 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -4082,16 +4184,26 @@
nvidia,bpmp = <&bpmp 3>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pci@8460000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xc0 0xb0000000 0x0 0x10000000>,
<0x00 0x08460000 0x0 0x00004000>,
reg = <0x00 0x08460000 0x0 0x00004000>,
<0x00 0x08464000 0x0 0x00001000>,
<0x00 0x08465000 0x0 0x00001000>,
<0x00 0x08470000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08470000 0x0 0x00010000>,
<0xc0 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -4114,16 +4226,26 @@
nvidia,bpmp = <&bpmp 4>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
pci@8480000 {
compatible = "nvidia,tegra264-pcie";
reg = <0xc8 0xb0000000 0x0 0x10000000>,
<0x00 0x08480000 0x0 0x00004000>,
reg = <0x00 0x08480000 0x0 0x00004000>,
<0x00 0x08484000 0x0 0x00001000>,
<0x00 0x08485000 0x0 0x00001000>,
<0x00 0x08490000 0x0 0x00010000>;
reg-names = "ecam", "xal", "xtl", "xtl-pri", "xpl";
<0x00 0x08490000 0x0 0x00010000>,
<0xc8 0xb0000000 0x0 0x10000000>;
reg-names = "xal", "xtl", "xtl-pri", "xpl", "ecam";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
@@ -4146,6 +4268,16 @@
nvidia,bpmp = <&bpmp 5>;
status = "disabled";
pcie@0 {
device_type = "pci";
compatible = "pciclass,0604";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
};
};
};
arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts
-18
View File
@@ -90,10 +90,6 @@
};
&gpio0 {
interrupts = <13>, <14>, <15>, <16>,
<17>, <18>, <19>, <20>,
<21>, <22>, <23>, <24>,
<25>, <26>;
ngpios = <14>;
gpio-line-names = "", "", "", "", "", "", "",
"", "", "", "", "", "SD_CARD_CS", "USER_BUTTON";
@@ -101,12 +97,6 @@
};
&gpio1 {
interrupts = <27>, <28>, <29>, <30>,
<31>, <32>, <33>, <34>,
<35>, <36>, <37>, <38>,
<39>, <40>, <41>, <42>,
<43>, <44>, <45>, <46>,
<47>, <48>, <49>, <50>;
ngpios = <24>;
gpio-line-names = "", "", "", "", "", "", "", "", "", "",
"", "", "", "", "", "", "", "", "", "",
@@ -115,14 +105,6 @@
};
&gpio2 {
interrupts = <53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>,
<53>, <53>, <53>, <53>;
ngpios = <32>;
gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2",
"P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5",
drivers/soc/tegra/fuse/tegra-apbmisc.c
+1 -1
View File
@@ -309,7 +309,7 @@ void tegra_acpi_init_apbmisc(void)
ret = acpi_dev_get_memory_resources(adev, &resource_list);
if (ret < 0) {
pr_err("failed to get APBMISC memory resources");
pr_err("failed to get APBMISC memory resources\n");
goto out_put_acpi_dev;
}
drivers/soc/tegra/pmc.c
+1
View File
@@ -3151,6 +3151,7 @@ static int tegra_pmc_probe(struct platform_device *pdev)
#if defined(CONFIG_ARM)
mutex_lock(&early_pmc->powergates_lock);
early_pmc->rate = pmc->rate;
iounmap(early_pmc->base);
early_pmc->base = pmc->base;
mutex_unlock(&early_pmc->powergates_lock);