mtd: mtd_intel_dg: reset poll counter for each erase

The non-posted erase polling counter is initialized only once per MTD
erase request. Large requests therefore share the polling budget across
all 4K erase commands and can fail with -ETIME even though no individual
command timed out.

Reset the counter for each 4K erase command so every operation gets the
intended completion timeout.

Cc: [email protected]
Fixes: a1c940cbf5 ("drm/xe/nvm: add support for non-posted erase")
Signed-off-by: Menachem Adin <[email protected]>
Signed-off-by: Alexander Usyskin <[email protected]>
Signed-off-by: Miquel Raynal <[email protected]>
This commit is contained in:
Menachem Adin authored and Miquel Raynal committed 2026-09-04 20:32:21 +02:00
1 parent 39b975ff20
commit 200c32e3cd
1 file changed
+2 -1
+2 -1
View File
@@ -387,7 +387,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a
void __iomem *base2 = nvm->base2;
void __iomem *base = nvm->base;
const u32 block = 0x10;
u32 iter = 0;
u32 iter;
u32 reg;
u64 i;
@@ -396,6 +396,7 @@ idg_erase(struct intel_dg_nvm *nvm, u8 region, loff_t from, u64 len, u64 *fail_a
iowrite32(region << 24 | block, base + NVM_ERASE_REG);
if (nvm->non_posted_erase) {
/* Wait for Erase Done */
iter = 0;
reg = ioread32(base2 + NVM_DEBUG_REG);
while (!(reg & NVM_NON_POSTED_ERASE_DONE) &&
++iter < NVM_NON_POSTED_ERASE_DONE_ITER) {