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Justin Hibbits
fd8d34ce27
The NCSW reference base requires tuning for each target, and currently
is configured for FMANv2. This doesn't readily work on FMANv3 devices,
such as the T-series powerpc, or the LS1043 ARM. Since Freescale/NXP
abandoned the NCSW driver a decade ago, it makes sense to abandon it
ourselves as well. This new driver uses a combination of the NCSW
driver and the Linux driver (BSD/GPL dual licensed) as a reference, but
contains no actual code from them.
The DPAA (Data Path Acceleration Architecture) subsystem consists of the
following components:
* BMan -- Buffer Manager. Manages buffer pools of different sizes (one
size per pool, up to 64 pools)
* QMan -- Queue Manager. Manages the interfaces between DPAA-based
components and the CPU(s).
* FMan -- Frame Manager. Responsible for all ethernet-related
processing. Consists itself of the following components:
* Ports -- interfaces to the QMan. An ethernet interface consists of
2 ports.
Ports use "Next-invoked action" (NIA) descriptors to form a pipeline
for processing on receive and transmit.
* Parser -- performs protocol header parsing and validation. Both
hardware and software parsers are available.
* KeyGen -- Key generator, used to start the classification process
(for the Policer), generating FQIDs and other keys based on the
frame input.
* Policer -- performs traffic shaping and classification
* MAC -- SoC specific ethernet MAC (dTSEC, TGEC, mEMAC). Currently
supports dTSEC and mEMAC, along with their MDIO blocks.
Additional components not yet handled:
SEC -- Security engine (crypto)
RE -- RAID engine
RapidIO
DCE -- Decompression/Compression engine, supports ZLIB, DEFLATE, and
GZIP, as well as base64 encoding and decoding.
BMan and QMan are accessed via cache-coherent portals, using ring
buffers as I/O. The intent is for portals to be per-CPU (core/thread)
to reduce locking contention and improve performance. This driver pins
interrupt handlers to the CPU "owning" a given portal, and uses critical
sections to prevent switching while accessing the portal.
87 lines
2.9 KiB
C
87 lines
2.9 KiB
C
/*-
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* Copyright (c) 2012 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/proc.h>
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#include <sys/pcpu.h>
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#include <sys/rman.h>
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#include <sys/sched.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/resource.h>
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#include <machine/tlb.h>
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#include "portals.h"
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int
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dpaa_portal_alloc_res(device_t dev, int cpu)
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{
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struct dpaa_portal_softc *sc = device_get_softc(dev);
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sc->sc_mres[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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0, RF_ACTIVE);
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if (sc->sc_mres[0] == NULL) {
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device_printf(dev,
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"Could not allocate cache enabled memory.\n");
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return (ENXIO);
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}
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/* Cache inhibited area */
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sc->sc_mres[1] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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1, RF_ACTIVE);
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if (sc->sc_mres[1] == NULL) {
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device_printf(dev,
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"Could not allocate cache inhibited memory.\n");
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mres[0]);
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return (ENXIO);
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}
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sc->sc_dev = dev;
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sc->sc_ce_va = rman_get_bushandle(sc->sc_mres[0]);
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sc->sc_ce_size = rman_get_size(sc->sc_mres[0]);
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sc->sc_ce_pa = pmap_kextract(sc->sc_ce_va);
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sc->sc_ci_va = rman_get_bushandle(sc->sc_mres[1]);
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sc->sc_ci_size = rman_get_size(sc->sc_mres[1]);
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sc->sc_ci_pa = pmap_kextract(sc->sc_ci_va);
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tlb1_set_entry(sc->sc_ce_va, sc->sc_ce_pa, sc->sc_ce_size,
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_TLB_ENTRY_MEM | _TLB_ENTRY_SHARED);
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sc->sc_ires = bus_alloc_resource_any(dev, SYS_RES_IRQ, 0, RF_ACTIVE);
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/* Allocate interrupts */
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if (sc->sc_ires == NULL) {
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device_printf(dev, "Could not allocate irq.\n");
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return (ENXIO);
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}
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return (0);
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}
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