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Justin Hibbits
fd8d34ce27
The NCSW reference base requires tuning for each target, and currently
is configured for FMANv2. This doesn't readily work on FMANv3 devices,
such as the T-series powerpc, or the LS1043 ARM. Since Freescale/NXP
abandoned the NCSW driver a decade ago, it makes sense to abandon it
ourselves as well. This new driver uses a combination of the NCSW
driver and the Linux driver (BSD/GPL dual licensed) as a reference, but
contains no actual code from them.
The DPAA (Data Path Acceleration Architecture) subsystem consists of the
following components:
* BMan -- Buffer Manager. Manages buffer pools of different sizes (one
size per pool, up to 64 pools)
* QMan -- Queue Manager. Manages the interfaces between DPAA-based
components and the CPU(s).
* FMan -- Frame Manager. Responsible for all ethernet-related
processing. Consists itself of the following components:
* Ports -- interfaces to the QMan. An ethernet interface consists of
2 ports.
Ports use "Next-invoked action" (NIA) descriptors to form a pipeline
for processing on receive and transmit.
* Parser -- performs protocol header parsing and validation. Both
hardware and software parsers are available.
* KeyGen -- Key generator, used to start the classification process
(for the Policer), generating FQIDs and other keys based on the
frame input.
* Policer -- performs traffic shaping and classification
* MAC -- SoC specific ethernet MAC (dTSEC, TGEC, mEMAC). Currently
supports dTSEC and mEMAC, along with their MDIO blocks.
Additional components not yet handled:
SEC -- Security engine (crypto)
RE -- RAID engine
RapidIO
DCE -- Decompression/Compression engine, supports ZLIB, DEFLATE, and
GZIP, as well as base64 encoding and decoding.
BMan and QMan are accessed via cache-coherent portals, using ring
buffers as I/O. The intent is for portals to be per-CPU (core/thread)
to reduce locking contention and improve performance. This driver pins
interrupt handlers to the CPU "owning" a given portal, and uses critical
sections to prevent switching while accessing the portal.
205 lines
5.0 KiB
C
205 lines
5.0 KiB
C
/*-
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* Copyright (c) 2016 Justin Hibbits
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bus.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/socket.h>
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#include <machine/bus.h>
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#include <net/if.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <net/if_var.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "fman.h"
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#include "miibus_if.h"
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#define MDIO_LOCK() mtx_lock(&sc->sc_lock)
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#define MDIO_UNLOCK() mtx_unlock(&sc->sc_lock)
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#define MDIO_WRITE4(sc, r, v) \
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bus_write_4(sc->sc_res, r, v)
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#define MDIO_READ4(sc, r) \
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bus_read_4(sc->sc_res, r)
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#define MDIO_MIIMCFG 0x0
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#define MDIO_MIIMCOM 0x4
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#define MIIMCOM_SCAN_CYCLE 0x00000002
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#define MIIMCOM_READ_CYCLE 0x00000001
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#define MDIO_MIIMADD 0x8
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#define MDIO_MIIMCON 0xc
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#define MDIO_MIIMSTAT 0x10
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#define MDIO_MIIMIND 0x14
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#define MIIMIND_BUSY 0x1
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static int pqmdio_fdt_probe(device_t dev);
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static int pqmdio_fdt_attach(device_t dev);
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static int pqmdio_detach(device_t dev);
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static int pqmdio_miibus_readreg(device_t dev, int phy, int reg);
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static int pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value);
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struct pqmdio_softc {
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struct mtx sc_lock;
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struct resource *sc_res;
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};
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static device_method_t pqmdio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pqmdio_fdt_probe),
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DEVMETHOD(device_attach, pqmdio_fdt_attach),
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DEVMETHOD(device_detach, pqmdio_detach),
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/* MII interface */
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DEVMETHOD(miibus_readreg, pqmdio_miibus_readreg),
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DEVMETHOD(miibus_writereg, pqmdio_miibus_writereg),
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DEVMETHOD_END
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};
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static struct ofw_compat_data mdio_compat_data[] = {
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{"fsl,fman-mdio", 0},
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{NULL, 0}
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};
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static driver_t pqmdio_driver = {
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"pq_mdio",
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pqmdio_methods,
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sizeof(struct pqmdio_softc),
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};
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static int
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pqmdio_fdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, mdio_compat_data)->ocd_str)
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return (ENXIO);
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device_set_desc(dev, "Freescale QorIQ MDIO");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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pqmdio_fdt_attach(device_t dev)
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{
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struct pqmdio_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 0, RF_ACTIVE);
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OF_device_register_xref(OF_xref_from_node(ofw_bus_get_node(dev)), dev);
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mtx_init(&sc->sc_lock, device_get_nameunit(dev), "QorIQ MDIO lock",
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MTX_DEF);
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return (0);
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}
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static int
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pqmdio_detach(device_t dev)
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{
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struct pqmdio_softc *sc;
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sc = device_get_softc(dev);
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mtx_destroy(&sc->sc_lock);
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return (0);
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}
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int
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pqmdio_miibus_readreg(device_t dev, int phy, int reg)
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{
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struct pqmdio_softc *sc;
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int rv;
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sc = device_get_softc(dev);
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MDIO_LOCK();
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MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);
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MDIO_WRITE4(sc, MDIO_MIIMCOM, MIIMCOM_READ_CYCLE);
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MDIO_READ4(sc, MDIO_MIIMCOM);
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while ((MDIO_READ4(sc, MDIO_MIIMIND)) & MIIMIND_BUSY)
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;
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rv = MDIO_READ4(sc, MDIO_MIIMSTAT);
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MDIO_WRITE4(sc, MDIO_MIIMCOM, 0);
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MDIO_READ4(sc, MDIO_MIIMCOM);
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MDIO_UNLOCK();
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return (rv);
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}
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int
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pqmdio_miibus_writereg(device_t dev, int phy, int reg, int value)
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{
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struct pqmdio_softc *sc;
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sc = device_get_softc(dev);
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MDIO_LOCK();
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/* Stop the MII management read cycle */
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MDIO_WRITE4(sc, MDIO_MIIMCOM, 0);
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MDIO_READ4(sc, MDIO_MIIMCOM);
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MDIO_WRITE4(sc, MDIO_MIIMADD, (phy << 8) | reg);
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MDIO_WRITE4(sc, MDIO_MIIMCON, value);
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MDIO_READ4(sc, MDIO_MIIMCON);
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/* Wait till MII management write is complete */
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while ((MDIO_READ4(sc, MDIO_MIIMIND)) & MIIMIND_BUSY)
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;
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MDIO_UNLOCK();
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return (0);
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}
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EARLY_DRIVER_MODULE(pqmdio, fman, pqmdio_driver, 0, 0,
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BUS_PASS_SUPPORTDEV);
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DRIVER_MODULE(miibus, pqmdio, miibus_driver, 0, 0);
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MODULE_DEPEND(pqmdio, miibus, 1, 1, 1);
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