Yong Zhao 15426dbb65 drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9 ...

CWSR fails on Raven if the control stack is MTYPE_UC, which is used
for regular GART mappings. As a workaround we map it using MTYPE_NC.

The MEC firmware expects the control stack at one page offset from the
start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU
added a memory allocation flag just for this purpose.

Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Yong Zhao <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>

2018-09-20 10:25:17 -05:00

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asic_reg

drm/amdgpu: add more jpeg register offset headers

2018-06-15 12:20:35 -05:00

ivsrcid

drm/amd: Add interrupt source definitions for SOC15 v3.

2018-07-13 14:45:37 -05:00

linux

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amd_acpi.h

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amd_pcie_helpers.h

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amd_pcie.h

drm/amdgpu: update amd_pcie.h to include gen4 speeds

2018-07-05 16:39:59 -05:00

amd_shared.h

drm/amd: Add sphinx documentation for amd_ip_funcs

2018-07-05 16:57:54 -05:00

atom-bits.h

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atom-names.h

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atom-types.h

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atombios.h

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atomfirmware.h

drm/amd: Add missing fields in atom_integrated_system_info_v1_11

2018-07-27 09:07:43 -05:00

atomfirmwareid.h

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cgs_common.h

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cik_structs.h

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displayobject.h

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dm_pp_interface.h

drm/amd/pp: Remove the same struct define in powerplay

2018-07-05 16:40:02 -05:00

kgd_kfd_interface.h

drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9

2018-09-20 10:25:17 -05:00

kgd_pp_interface.h

drm/amd/pp: Export notify_smu_enable_pwe to display

2018-07-05 16:40:00 -05:00

pptable.h

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soc15_hw_ip.h

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soc15_ih_clientid.h

drm/amdgpu/vg20:Add IH client ID for the 2nd UVD

2018-05-18 16:08:13 -05:00

v9_structs.h

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vega10_enum.h

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vega10_ip_offset.h

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vega20_ip_offset.h

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vi_structs.h

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