mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-10-31 14:23:49 +01:00
Christoph Hellwig
885f7f8e30
The function currently known as flush_icache_user_range only operates on a single page. Rename it to flush_icache_user_page as we'll need the name flush_icache_user_range for something else soon. Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Acked-by: Geert Uytterhoeven <[email protected]> Cc: Richard Henderson <[email protected]> Cc: Ivan Kokshaysky <[email protected]> Cc: Matt Turner <[email protected]> Cc: Tony Luck <[email protected]> Cc: Fenghua Yu <[email protected]> Cc: Geert Uytterhoeven <[email protected]> Cc: Greentime Hu <[email protected]> Cc: Vincent Chen <[email protected]> Cc: Jonas Bonn <[email protected]> Cc: Stefan Kristiansson <[email protected]> Cc: Stafford Horne <[email protected]> Cc: Benjamin Herrenschmidt <[email protected]> Cc: Paul Mackerras <[email protected]> Cc: Michael Ellerman <[email protected]> Cc: Paul Walmsley <[email protected]> Cc: Palmer Dabbelt <[email protected]> Cc: Albert Ou <[email protected]> Cc: Arnd Bergmann <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Arnaldo Carvalho de Melo <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Namhyung Kim <[email protected]> Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Linus Torvalds <[email protected]>
74 lines
2.2 KiB
C
74 lines
2.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* OpenRISC implementation:
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* Copyright (C) Jan Henrik Weinstock <[email protected]>
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* et al.
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*/
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#ifndef __ASM_CACHEFLUSH_H
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#define __ASM_CACHEFLUSH_H
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#include <linux/mm.h>
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/*
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* Helper function for flushing or invalidating entire pages from data
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* and instruction caches. SMP needs a little extra work, since we need
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* to flush the pages on all cpus.
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*/
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extern void local_dcache_page_flush(struct page *page);
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extern void local_icache_page_inv(struct page *page);
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/*
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* Data cache flushing always happen on the local cpu. Instruction cache
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* invalidations need to be broadcasted to all other cpu in the system in
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* case of SMP configurations.
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*/
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#ifndef CONFIG_SMP
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) local_icache_page_inv(page)
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#else /* CONFIG_SMP */
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#define dcache_page_flush(page) local_dcache_page_flush(page)
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#define icache_page_inv(page) smp_icache_page_inv(page)
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extern void smp_icache_page_inv(struct page *page);
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#endif /* CONFIG_SMP */
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/*
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* Synchronizes caches. Whenever a cpu writes executable code to memory, this
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* should be called to make sure the processor sees the newly written code.
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*/
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static inline void sync_icache_dcache(struct page *page)
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{
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if (!IS_ENABLED(CONFIG_DCACHE_WRITETHROUGH))
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dcache_page_flush(page);
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icache_page_inv(page);
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}
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/*
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* Pages with this bit set need not be flushed/invalidated, since
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* they have not changed since last flush. New pages start with
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* PG_arch_1 not set and are therefore dirty by default.
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*/
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#define PG_dc_clean PG_arch_1
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#define ARCH_IMPLEMENTS_FLUSH_DCACHE_PAGE 1
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static inline void flush_dcache_page(struct page *page)
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{
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clear_bit(PG_dc_clean, &page->flags);
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}
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#define flush_icache_user_page(vma, page, addr, len) \
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do { \
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if (vma->vm_flags & VM_EXEC) \
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sync_icache_dcache(page); \
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} while (0)
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#include <asm-generic/cacheflush.h>
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#endif /* __ASM_CACHEFLUSH_H */
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