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On the at91_adc a minimal Sample and Hold Time is necessary for the ADC to guarantee the best converted final value between two channels selection. This time has to be programmed through the bitfield SHTIM in the Mode Register ADC_MR. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <[email protected]> Signed-off-by: Ludovic Desroches <[email protected]> Signed-off-by: Jonathan Cameron <[email protected]>