Marek Vasut f7f9abc5ea phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED ...

The 'fsl,refclk-pad-mode' DT property used to select clock source for
PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT,
IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first
two options are handled correctly by the driver, the last one is not,
this patch implements support for the last option.

The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input,
the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC
internal PLL and output to PCIE_RESREF external IO pin. The last
IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY
clock are sourced from SoC internal PLL and not output anywhere.

Reviewed-by: Richard Zhu <[email protected]>
Signed-off-by: Marek Vasut <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Kishon Vijay Abraham I <[email protected]>
Cc: Marcel Ziswiler <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Richard Zhu <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Vinod Koul <[email protected]>
Cc: [email protected]
To: [email protected]
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>

2022-04-20 14:45:55 +05:30

..

Kconfig

phy: PHY_FSL_LYNX_28G should depend on ARCH_LAYERSCAPE

2022-03-29 08:45:16 -07:00

Makefile

…

phy-fsl-imx8-mipi-dphy.c

phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support

2022-04-20 12:59:50 +05:30

phy-fsl-imx8m-pcie.c

phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED

2022-04-20 14:45:55 +05:30

phy-fsl-imx8mq-usb.c

…

phy-fsl-lynx-28g.c

…