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Serge Semin
f9f890ba2b
Add a new macro DWAPB_MAX_GPIOS which defines the maximum possible number of GPIO lines corresponding to the maximum DW APB GPIO controller port width. Use the new macro instead of number literal 32 where it's applicable. Suggested-by: Andy Shevchenko <[email protected]> Signed-off-by: Serge Semin <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Linus Walleij <[email protected]>
26 lines
445 B
C
26 lines
445 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright(c) 2014 Intel Corporation.
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*/
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#ifndef GPIO_DW_APB_H
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#define GPIO_DW_APB_H
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#define DWAPB_MAX_GPIOS 32
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struct dwapb_port_property {
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struct fwnode_handle *fwnode;
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unsigned int idx;
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unsigned int ngpio;
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unsigned int gpio_base;
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int irq[DWAPB_MAX_GPIOS];
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bool irq_shared;
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};
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struct dwapb_platform_data {
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struct dwapb_port_property *properties;
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unsigned int nports;
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};
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#endif
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