Kunihiko Hayashi 1ec09a2ec6 clk: uniphier: Add SCSSI clock gate for each channel ...

SCSSI has clock gates for each channel in the SoCs newer than Pro4,
so this adds missing clock gates for channel 1, 2 and 3. And more, this
moves MCSSI clock ID after SCSSI.

Fixes: ff388ee365 ("clk: uniphier: add clock frequency support for SPI")
Signed-off-by: Kunihiko Hayashi <[email protected]>
Acked-by: Masahiro Yamada <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>

2020-01-04 23:14:22 -08:00

..

clk-uniphier-core.c

drivers/clk: convert VL struct to struct_size

2019-11-08 08:36:12 -08:00

clk-uniphier-cpugear.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-fixed-factor.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-fixed-rate.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-gate.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-mio.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-mux.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier-peri.c

clk: uniphier: Add SCSSI clock gate for each channel

2020-01-04 23:14:22 -08:00

clk-uniphier-sys.c

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

clk-uniphier.h

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157

2019-05-30 11:26:37 -07:00

Kconfig

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Makefile

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