Tudor Ambarus fbf7e5ce40 mailbox: add Samsung Exynos driver ...

The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messages. When the controller is used by the
ACPM interface the shared register is ignored and the mailbox controller
acts as a doorbell. The controller just raises the interrupt to APM
after the ACPM interface has written the message to SRAM.

Add support for the Samsung Exynos mailbox controller.

Signed-off-by: Tudor Ambarus <[email protected]>
Signed-off-by: Jassi Brar <[email protected]>

2025-01-18 16:18:48 -06:00

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arm_mhuv2_message.h

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brcm-message.h

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exynos-message.h

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mchp-ipc.h

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mtk-cmdq-mailbox.h

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zynqmp-ipi-message.h

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