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When using simultaneously the two DMA channels on a same engine, some transfers are never completed. For example, an endless lock can occur while writing heavily on a RAID5 array (with async-tx offload support enabled). Note that this issue can also be reproduced by using the DMA test client. On a same engine, the interrupt cause register is shared between two DMA channels. This patch make sure that the cause bit is only cleared for the requested channel. Signed-off-by: Simon Guinot <[email protected]> Tested-by: Luc Saillard <[email protected]> Acked-by: saeed bishara <[email protected]> Cc: <[email protected]> Signed-off-by: Dan Williams <[email protected]>