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Hiroshi DOYU
87d0bab2cb
Tegra AHB Bus conforms to the AMBA Specification (Rev 2.0) Advanced High-performance Bus (AHB) architecture. The AHB Arbiter controls AHB bus master arbitration. This effectively forms a second level of arbitration for access to the memory controller through the AHB Slave Memory device. The AHB pre-fetch logic can be configured to enhance performance for devices doing sequential access. Each AHB master is assigned to either the high or low priority bin. Both Tegra20/30 have this AHB bus. Some of configuration params could be passed from DT too if needed. Signed-off-by: Hiroshi DOYU <[email protected]> Acked-by: Arnd Bergmann <[email protected]> Cc: Felipe Balbi <[email protected]> Signed-off-by: Stephen Warren <[email protected]>
3 lines
73 B
Makefile
3 lines
73 B
Makefile
obj-$(CONFIG_ARM_AMBA) += bus.o
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obj-$(CONFIG_TEGRA_AHB) += tegra-ahb.o
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