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ENDPTFLUSH and ENDPTPRIME registers are set by software and clear by hardware. There is a bit for each endpoint. When we are setting a bit for an endpoint we should make sure we do not touch other endpoint bit. There is a race condition if the hardware clear the bit between the read and the write in hw_write. Cc: stable <[email protected]> # 3.11+ Signed-off-by: Peter Chen <[email protected]> Signed-off-by: Matthieu CASTET <[email protected]> Tested-by: Michael Grzeschik <[email protected]> Signed-off-by: Greg Kroah-Hartman <[email protected]>