Mark Tomlinson 97e914b7de MIPS: cavium_octeon: Fix syncw generation. ...

The Cavium Octeon CPU uses a special sync instruction for implementing
wmb, and due to a CPU bug, the instruction must appear twice. A macro
had been defined to hide this:

 #define __SYNC_rpt(type)     (1 + (type == __SYNC_wmb))

which was intended to evaluate to 2 for __SYNC_wmb, and 1 for any other
type of sync. However, this expression is evaluated by the assembler,
and not the compiler, and the result of '==' in the assembler is 0 or
-1, not 0 or 1 as it is in C. The net result was wmb() producing no code
at all. The simple fix in this patch is to change the '+' to '-'.

Fixes: bf92927251 ("MIPS: barrier: Add __SYNC() infrastructure")
Signed-off-by: Mark Tomlinson <[email protected]>
Tested-by: Chris Packham <[email protected]>
Signed-off-by: Paul Burton <[email protected]>
Cc: [email protected]
Cc: [email protected]

2020-02-15 12:44:03 -08:00

..

asm

MIPS: cavium_octeon: Fix syncw generation.

2020-02-15 12:44:03 -08:00

uapi/asm

arch: sembuf.h: make uapi asm/sembuf.h self-contained

2019-12-04 19:44:14 -08:00