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Implement a USB2PHY port reset driver for the Renesas RZ/V2H(P) SoC. Enable control of USB2.0 PHY reset and power-down operations, including assert and deassert functionalities for the PHY. Leverage device tree (OF) data to support future SoCs with similar USB2PHY hardware but varying register configurations. Define initialization values and control register settings to ensure flexibility for upcoming platforms. Signed-off-by: Lad Prabhakar <[email protected]> Reviewed-by: Biju Das <[email protected]> Reviewed-by: Fabrizio Castro <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Philipp Zabel <[email protected]>