mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-10-30 13:52:50 +01:00
Ross Philipson
5467ade151
These are definitions for TPM 2.0 interface and interactions with the platform as defined in the TCG specification: These definitions are located here in a separate file to avoid conflicts with vendor specific TIS/FIFO definition (e.g. STMicroelectronics, Infineon Technologies, etc). This allows the TCG defined TIS/FIFO interface to be in a public header while the former chip specific implementations contain their own definitions. TPM 1.x family chips that adhere to the TCG specifications use the TIS/FIFO interface as defined here. TCG PC Client Platform TPM Profile (PTP) Specification - https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/ Co-developed-by: Daniel P. Smith <[email protected]> Signed-off-by: Daniel P. Smith <[email protected]> Co-developed-by: Alec Brown <[email protected]> Signed-off-by: Alec Brown <[email protected]> Signed-off-by: Ross Philipson <[email protected]> Reviewed-by: Jarkko Sakkinen <[email protected]> Signed-off-by: Jarkko Sakkinen <[email protected]>
134 lines
4.2 KiB
C
134 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Following copyright information was take from the original file
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* <drivers/char/tpm/tpm_tis_core.h> where the definitions were moved
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* from:
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*
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* Copyright (C) 2005, 2006 IBM Corporation
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* Copyright (C) 2014, 2015 Intel Corporation
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*
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* Authors:
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* Leendert van Doorn <[email protected]>
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* Kylene Hall <[email protected]>
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*
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* Maintained by: <[email protected]>
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*
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* Device driver for TCG/TCPA TPM (trusted platform module).
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* Specifications at www.trustedcomputinggroup.org
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*
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* This device driver implements the TPM interface as defined in
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* the TCG TPM Interface Spec version 1.2, revision 1.0.
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*/
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#ifndef __LINUX_TPM_PTP_H__
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#define __LINUX_TPM_PTP_H__
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/*
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* TCG PC Client Platform TPM Profile (PTP) Specification
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* https://trustedcomputinggroup.org/resource/pc-client-platform-tpm-profile-ptp-specification/
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*/
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/* TIS/FIFO macros and definitions */
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enum tis_access {
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TPM_ACCESS_VALID = 0x80,
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TPM_ACCESS_ACTIVE_LOCALITY = 0x20, /* (R) */
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TPM_ACCESS_RELINQUISH_LOCALITY = 0x20, /* (W) */
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TPM_ACCESS_REQUEST_PENDING = 0x04, /* (W) */
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TPM_ACCESS_REQUEST_USE = 0x02, /* (W) */
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};
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enum tis_status {
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TPM_STS_VALID = 0x80, /* (R) */
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TPM_STS_COMMAND_READY = 0x40, /* (R) */
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TPM_STS_DATA_AVAIL = 0x10, /* (R) */
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TPM_STS_DATA_EXPECT = 0x08, /* (R) */
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TPM_STS_GO = 0x20, /* (W) */
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TPM_STS_RESPONSE_RETRY = 0x02, /* (R) */
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TPM_STS_READ_ZERO = 0x23, /* bits that must be zero on read */
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};
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enum tis_int_flags {
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TPM_GLOBAL_INT_ENABLE = 0x80000000,
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TPM_INTF_BURST_COUNT_STATIC = 0x100,
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TPM_INTF_CMD_READY_INT = 0x080,
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TPM_INTF_INT_EDGE_FALLING = 0x040,
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TPM_INTF_INT_EDGE_RISING = 0x020,
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TPM_INTF_INT_LEVEL_LOW = 0x010,
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TPM_INTF_INT_LEVEL_HIGH = 0x008,
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TPM_INTF_LOCALITY_CHANGE_INT = 0x004,
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TPM_INTF_STS_VALID_INT = 0x002,
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TPM_INTF_DATA_AVAIL_INT = 0x001,
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};
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enum tis_defaults {
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TIS_MEM_LEN = 0x5000,
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TIS_SHORT_TIMEOUT = 750, /* ms */
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TIS_LONG_TIMEOUT = 4000, /* 4 secs */
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TIS_TIMEOUT_MIN_ATML = 14700, /* usecs */
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TIS_TIMEOUT_MAX_ATML = 15000, /* usecs */
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};
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#define TIS_MEM_X86_LPC_BASE 0xFED40000
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#define INTEL_LEGACY_BLK_BASE_ADDR 0xFED08000
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enum tis_x86_defaults {
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TIS_MEM_X86_LEN = 0x5000,
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ILB_REMAP_SIZE = 0x100,
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LPC_CNTRL_OFFSET = 0x84,
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LPC_CLKRUN_EN = (1 << 2),
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};
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/*
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* Some timeout values are needed before it is known whether the chip is
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* TPM 1.0 or TPM 2.0.
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*/
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#define TIS_TIMEOUT_A_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_A)
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#define TIS_TIMEOUT_B_MAX max_t(int, TIS_LONG_TIMEOUT, TPM2_TIMEOUT_B)
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#define TIS_TIMEOUT_C_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_C)
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#define TIS_TIMEOUT_D_MAX max_t(int, TIS_SHORT_TIMEOUT, TPM2_TIMEOUT_D)
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#define TPM_ACCESS(l) (0x0000 | ((l) << 12))
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#define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12))
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#define TPM_INT_VECTOR(l) (0x000C | ((l) << 12))
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#define TPM_INT_STATUS(l) (0x0010 | ((l) << 12))
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#define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12))
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#define TPM_STS(l) (0x0018 | ((l) << 12))
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#define TPM_STS3(l) (0x001b | ((l) << 12))
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#define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12))
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#define TPM_INTF_ID(l) (0x0030 | ((l) << 12))
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#define TPM_DID_VID(l) (0x0F00 | ((l) << 12))
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#define TPM_RID(l) (0x0F04 | ((l) << 12))
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/* TPM HW Interface and Capabilities */
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#define TPM_TIS_INTF_ACTIVE 0x00
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#define TPM_CRB_INTF_ACTIVE 0x01
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#define TPM_INTID_INTERFACE_TYPE GENMASK(3, 0)
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#define TPM_INTID_INTERFACE_VERSION GENMASK(7, 4)
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#define TPM_INTID_CAP_LOCALITY BIT(8)
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#define TPM_INTID_CAP_TIS BIT(13)
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#define TPM_INTID_CAP_CRB BIT(14)
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#define TPM_INTID_CAP_IF_RES GENMASK(16, 15)
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#define TPM_INTID_INTERFACE_SELECTOR GENMASK(18, 17)
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#define TPM_INTID_INTF_SEL_LOCK BIT(19)
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#define TPM_TIS_INTF_12 0x00
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#define TPM_TIS_INTF_13 0x02
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#define TPM2_TIS_INTF_13 0x03
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#define TPM_INTF_DATA_AVAIL_INT_SUPPORT BIT(0)
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#define TPM_INTF_STS_VALID_INT_SUPPORT BIT(1)
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#define TPM_INTF_LOCALITY_CHANGE_INT_SUPPORT BIT(2)
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#define TPM_INTF_INTERRUPT_LEVEL_HIGH BIT(3)
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#define TPM_INTF_INTERRUPT_LEVEL_LOW BIT(4)
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#define TPM_INTF_INTERRUPT_EDGE_RISING BIT(5)
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#define TPM_INTF_INTERRUPT_EDGE_FALLING BIT(6)
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#define TPM_INTF_COMMAND_READY_INT_SUPPORT BIT(7)
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#define TPM_INTF_BURST_COUNT_STATIC BIT(8)
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#define TPM_INTF_DATA_TRANSFER_SIZE_SUPPORT GENMASK(10, 9)
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#define TPM_INTF_INTERFACE_VERSION GENMASK(30, 28)
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#endif
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