mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-10-30 05:42:46 +01:00
Heikki Krogerus
874ef9a6f2
Moving the register definitions to a global header file include/linux/designware_i2c.h. That removes the need to duplicate them in the adaptation layers for this driver outside of drivers/i2c/busses/. There is at least one of those in drivers/gpu/drm/xe/xe_i2c.c. Suggested-by: Andy Shevchenko <[email protected]> Suggested-by: Raag Jadav <[email protected]> Reviewed-by: Raag Jadav <[email protected]> Reviewed-by: Mika Westerberg <[email protected]> Reviewed-by: Andy Shevchenko <[email protected]> Signed-off-by: Heikki Krogerus <[email protected]> Acked-by: Mika Westerberg <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Rodrigo Vivi <[email protected]> (cherry picked from commit 2ab2fb31411a494e4579dfacda986a2672f80e65) Signed-off-by: Rodrigo Vivi <[email protected]>
108 lines
3.2 KiB
C
108 lines
3.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Synopsys DesignWare I2C register definitions
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*
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* Copyright (C) 2026, Intel Corporation
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*/
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#ifndef __LINUX_DESIGNWARE_I2C_H
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#define __LINUX_DESIGNWARE_I2C_H
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#include <linux/bits.h>
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/*
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* Registers offset
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*/
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#define DW_IC_CON 0x00
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#define DW_IC_TAR 0x04
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#define DW_IC_SAR 0x08
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#define DW_IC_DATA_CMD 0x10
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#define DW_IC_SS_SCL_HCNT 0x14
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#define DW_IC_SS_SCL_LCNT 0x18
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#define DW_IC_FS_SCL_HCNT 0x1c
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#define DW_IC_FS_SCL_LCNT 0x20
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#define DW_IC_HS_SCL_HCNT 0x24
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#define DW_IC_HS_SCL_LCNT 0x28
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#define DW_IC_INTR_STAT 0x2c
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#define DW_IC_INTR_MASK 0x30
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#define DW_IC_RAW_INTR_STAT 0x34
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#define DW_IC_RX_TL 0x38
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#define DW_IC_TX_TL 0x3c
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#define DW_IC_CLR_INTR 0x40
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#define DW_IC_CLR_RX_UNDER 0x44
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#define DW_IC_CLR_RX_OVER 0x48
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#define DW_IC_CLR_TX_OVER 0x4c
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#define DW_IC_CLR_RD_REQ 0x50
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#define DW_IC_CLR_TX_ABRT 0x54
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#define DW_IC_CLR_RX_DONE 0x58
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#define DW_IC_CLR_ACTIVITY 0x5c
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#define DW_IC_CLR_STOP_DET 0x60
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#define DW_IC_CLR_START_DET 0x64
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#define DW_IC_CLR_GEN_CALL 0x68
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#define DW_IC_ENABLE 0x6c
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#define DW_IC_STATUS 0x70
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#define DW_IC_TXFLR 0x74
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#define DW_IC_RXFLR 0x78
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#define DW_IC_SDA_HOLD 0x7c
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#define DW_IC_TX_ABRT_SOURCE 0x80
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#define DW_IC_ENABLE_STATUS 0x9c
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#define DW_IC_CLR_RESTART_DET 0xa8
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#define DW_IC_SMBUS_INTR_STAT 0xc8
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#define DW_IC_SMBUS_INTR_MASK 0xcc
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#define DW_IC_CLR_SMBUS_INTR 0xd4
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#define DW_IC_COMP_PARAM_1 0xf4
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#define DW_IC_COMP_VERSION 0xf8
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#define DW_IC_COMP_TYPE 0xfc
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/* DW_IC_CON bits */
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#define DW_IC_CON_MASTER BIT(0)
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#define DW_IC_CON_SPEED_STD (1 << 1)
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#define DW_IC_CON_SPEED_FAST (2 << 1)
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#define DW_IC_CON_SPEED_HIGH (3 << 1)
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#define DW_IC_CON_SPEED_MASK GENMASK(2, 1)
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#define DW_IC_CON_10BITADDR_SLAVE BIT(3)
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#define DW_IC_CON_10BITADDR_MASTER BIT(4)
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#define DW_IC_CON_RESTART_EN BIT(5)
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#define DW_IC_CON_SLAVE_DISABLE BIT(6)
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#define DW_IC_CON_STOP_DET_IFADDRESSED BIT(7)
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#define DW_IC_CON_TX_EMPTY_CTRL BIT(8)
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#define DW_IC_CON_RX_FIFO_FULL_HLD_CTRL BIT(9)
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#define DW_IC_CON_BUS_CLEAR_CTRL BIT(11)
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/* DW_IC_DATA_CMD bits */
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#define DW_IC_DATA_CMD_DAT GENMASK(7, 0)
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#define DW_IC_DATA_CMD_FIRST_DATA_BYTE BIT(11)
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/* DW_IC_INTR_* bits */
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#define DW_IC_INTR_RX_UNDER BIT(0)
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#define DW_IC_INTR_RX_OVER BIT(1)
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#define DW_IC_INTR_RX_FULL BIT(2)
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#define DW_IC_INTR_TX_OVER BIT(3)
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#define DW_IC_INTR_TX_EMPTY BIT(4)
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#define DW_IC_INTR_RD_REQ BIT(5)
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#define DW_IC_INTR_TX_ABRT BIT(6)
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#define DW_IC_INTR_RX_DONE BIT(7)
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#define DW_IC_INTR_ACTIVITY BIT(8)
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#define DW_IC_INTR_STOP_DET BIT(9)
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#define DW_IC_INTR_START_DET BIT(10)
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#define DW_IC_INTR_GEN_CALL BIT(11)
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#define DW_IC_INTR_RESTART_DET BIT(12)
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#define DW_IC_INTR_MST_ON_HOLD BIT(13)
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/* DW_IC_ENABLE bits */
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#define DW_IC_ENABLE_ENABLE BIT(0)
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#define DW_IC_ENABLE_ABORT BIT(1)
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/* DW_IC_STATUS bits */
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#define DW_IC_STATUS_ACTIVITY BIT(0)
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#define DW_IC_STATUS_TFE BIT(2)
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#define DW_IC_STATUS_RFNE BIT(3)
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#define DW_IC_STATUS_MASTER_ACTIVITY BIT(5)
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#define DW_IC_STATUS_SLAVE_ACTIVITY BIT(6)
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#define DW_IC_STATUS_MASTER_HOLD_TX_FIFO_EMPTY BIT(7)
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/* DW_IC_SMBUS_INTR_* bits */
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#define DW_IC_SMBUS_INTR_ALERT BIT(10)
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#endif /* __LINUX_DESIGNWARE_I2C_H */
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