mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-11-06 01:26:56 +01:00
Pull IOMMU updates from Joerg Roedel:
"Core:
- Detect scatterlist length overflows and finalize deferred domain
attachments before mapping MSI pages
- Consolidate x86 MSI reserved-region handling and clean up internal
DMA and SVA helpers
AMD IOMMU:
- Add IOMMU PerfOpt support, enabled by amdgpu for supported
integrated GPUs in identity domains
- Restrict forced identity mapping to GPUs that require it
- Fix kdump device-table allocation and reuse, ATS configuration
error handling, and an interrupt-remapping allocation leak
- Clean up device probing and initialization
- Add Vasant Hegde as an AMD IOMMU maintainer
ARM SMMUv2:
- Device-tree binding updates for Qualcomm Maili and Nord SoCs
ARM SMMUv3:
- Work around hardware integration issue on Google Tensor G5 SoCs
where all DMA transactions appear as instruction fetches
- Allow command queue size to be configured on the kernel
command-line
- Reduce queue sizes when running as a kdump kernel
- Fix some pre-existing issues in the driver and kunit tests reported
by Sashiko
- Fix handling of Arm hardware errata relating to the contiguous hint
when using SVA
- Rework the TLB invalidation logic in preparation for enabling
iommu-pt in future
- Minor cleanups in preparation for improving support for kdump
Apple DART:
- Support device-tree DMA aperture specifications
Broadcom:
- Add BCM2712 IOMMU support for Raspberry Pi 5 display and multimedia
devices, including the generic page-table format and shared TLB
cache management
Hyper-V:
- Add a para-virtualized guest IOMMU driver with guest-managed
stage-1 page tables and page-selective IOTLB invalidation
Intel VT-d:
- Enhanced IQE fault handling for batched multiple descriptors,
- Optimization of page-table level calculation in
compute_vasz_lg2_ss(),
- Fixes for several pre-existing issues reported by Sashiko,
- General cleanup and refinement
RISC-V:
- Report cache-coherency capability for coherent devices, enabling
VFIO/iommufd use
Samsung Exynos:
- Support SysMMUs without BLOCK mode, fixing their enable sequence
and TLB invalidation
- Improve v7 fault diagnostics with transaction information"
* tag 'iommu-updates-v7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux: (69 commits)
MAINTAINERS: Make Vasant Hegde AMD IOMMU maintainer
iommu/hyperv: Make hv_iommu_device static
iommu/hyperv: Add missing PCI dependency for the guest IOMMU driver
iommu/amd: Don't allocate kdump device table from DMA32
iommu/amd: Program device table when kdump reuse fails
iommu/dma: Clean up redundant MSI cookie check
iommu/dma: Catch scatterlist length overflows
iommu/hyperv: Add page-selective IOTLB flush support
iommu/hyperv: Add para-virtualized IOMMU support for Hyper-V guest
iommu/x86: Add architectural MSI reserved region helper
Drivers: hv: Add logical device ID registry for vPCI devices
hyperv: Introduce new hypercall interfaces used by Hyper-V guest IOMMU
iommu: Make iommu-dma helpers private
iommu/arm-smmu-v3: Don't rb_erase() a never-inserted stream node
iommu/arm-smmu-v3: Add Q_POS() macro
iommu/arm-smmu-v3: Add arm_smmu_attach_release()
iommu/arm-smmu-v3: Disable the impl before disabling the SMMU on shutdown
iommu/arm-smmu-v3: Populate the tlbi at the top of the call chain
iommu/arm-smmu-v3: Precompute the invalidation commands
iommu/arm-smmu-v3: Keep track in arm_smmu_invs if range invalidation is used
...
250 lines
6.5 KiB
C
250 lines
6.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* nested.c - nested mode translation support
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*
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* Copyright (C) 2023 Intel Corporation
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*
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* Author: Lu Baolu <[email protected]>
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* Jacob Pan <[email protected]>
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* Yi Liu <[email protected]>
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*/
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#define pr_fmt(fmt) "DMAR: " fmt
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#include <linux/iommu.h>
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#include <linux/pci.h>
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#include <linux/pci-ats.h>
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#include "iommu.h"
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#include "pasid.h"
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static int intel_nested_attach_dev(struct iommu_domain *domain,
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struct device *dev, struct iommu_domain *old)
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{
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struct device_domain_info *info = dev_iommu_priv_get(dev);
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struct dmar_domain *dmar_domain = to_dmar_domain(domain);
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struct intel_iommu *iommu = info->iommu;
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unsigned long flags;
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int ret = 0;
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device_block_translation(dev);
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/*
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* Stage-1 domain cannot work alone, it is nested on a s2_domain.
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* The s2_domain will be used in nested translation, hence needs
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* to ensure the s2_domain is compatible with this IOMMU.
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*/
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ret = paging_domain_compatible(&dmar_domain->s2_domain->domain, dev);
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if (ret) {
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dev_err_ratelimited(dev, "s2 domain is not compatible\n");
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return ret;
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}
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ret = domain_attach_iommu(dmar_domain, iommu);
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if (ret) {
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dev_err_ratelimited(dev, "Failed to attach domain to iommu\n");
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return ret;
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}
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ret = cache_tag_assign_domain(dmar_domain, dev, IOMMU_NO_PASID);
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if (ret)
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goto detach_iommu;
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ret = iopf_for_domain_set(domain, dev);
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if (ret)
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goto unassign_tag;
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ret = intel_pasid_setup_nested(iommu, dev,
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IOMMU_NO_PASID, dmar_domain);
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if (ret)
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goto disable_iopf;
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iopf_for_domain_remove(old, dev);
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info->domain = dmar_domain;
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info->domain_attached = true;
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spin_lock_irqsave(&dmar_domain->lock, flags);
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list_add(&info->link, &dmar_domain->devices);
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spin_unlock_irqrestore(&dmar_domain->lock, flags);
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return 0;
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disable_iopf:
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iopf_for_domain_remove(domain, dev);
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unassign_tag:
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cache_tag_unassign_domain(dmar_domain, dev, IOMMU_NO_PASID);
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detach_iommu:
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domain_detach_iommu(dmar_domain, iommu);
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return ret;
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}
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static void intel_nested_domain_free(struct iommu_domain *domain)
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{
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struct dmar_domain *dmar_domain = to_dmar_domain(domain);
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struct dmar_domain *s2_domain = dmar_domain->s2_domain;
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spin_lock(&s2_domain->s1_lock);
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list_del(&dmar_domain->s2_link);
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spin_unlock(&s2_domain->s1_lock);
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kfree(dmar_domain->qi_batch);
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kfree(dmar_domain);
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}
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static int intel_nested_cache_invalidate_user(struct iommu_domain *domain,
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struct iommu_user_data_array *array)
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{
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struct dmar_domain *dmar_domain = to_dmar_domain(domain);
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struct iommu_hwpt_vtd_s1_invalidate inv_entry;
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u32 processed = 0;
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int ret = 0;
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if (array->type != IOMMU_HWPT_INVALIDATE_DATA_VTD_S1) {
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ret = -EINVAL;
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goto out;
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}
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/*
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* The core re-invokes this op for the remaining requests, so handle one
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* request per call. A zero-length array only probes the type, validated
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* above.
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*/
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if (!array->entry_num)
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return 0;
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ret = iommu_copy_struct_from_user_array(
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&inv_entry, array, IOMMU_HWPT_INVALIDATE_DATA_VTD_S1, 0,
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__reserved);
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if (ret)
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goto out;
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if ((inv_entry.flags & ~IOMMU_VTD_INV_FLAGS_LEAF) ||
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inv_entry.__reserved) {
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ret = -EOPNOTSUPP;
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goto out;
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}
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if (!IS_ALIGNED(inv_entry.addr, VTD_PAGE_SIZE) ||
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(inv_entry.npages == U64_MAX && inv_entry.addr)) {
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ret = -EINVAL;
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goto out;
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}
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cache_tag_flush_range(dmar_domain, inv_entry.addr,
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inv_entry.addr +
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nrpages_to_size(inv_entry.npages) - 1,
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inv_entry.flags & IOMMU_VTD_INV_FLAGS_LEAF);
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processed = 1;
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out:
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array->entry_num = processed;
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return ret;
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}
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static int domain_setup_nested(struct intel_iommu *iommu,
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struct dmar_domain *domain,
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struct device *dev, ioasid_t pasid,
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struct iommu_domain *old)
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{
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if (old)
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intel_pasid_tear_down_entry(iommu, dev, pasid, false);
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return intel_pasid_setup_nested(iommu, dev, pasid, domain);
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}
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static int intel_nested_set_dev_pasid(struct iommu_domain *domain,
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struct device *dev, ioasid_t pasid,
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struct iommu_domain *old)
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{
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struct device_domain_info *info = dev_iommu_priv_get(dev);
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struct dmar_domain *dmar_domain = to_dmar_domain(domain);
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struct intel_iommu *iommu = info->iommu;
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struct dev_pasid_info *dev_pasid;
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int ret;
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if (!pasid_supported(iommu) || dev_is_real_dma_subdevice(dev))
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return -EOPNOTSUPP;
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if (context_copied(iommu, info->bus, info->devfn))
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return -EBUSY;
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ret = paging_domain_compatible(&dmar_domain->s2_domain->domain, dev);
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if (ret)
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return ret;
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dev_pasid = domain_add_dev_pasid(domain, dev, pasid);
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if (IS_ERR(dev_pasid))
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return PTR_ERR(dev_pasid);
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ret = iopf_for_domain_replace(domain, old, dev);
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if (ret)
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goto out_remove_dev_pasid;
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ret = domain_setup_nested(iommu, dmar_domain, dev, pasid, old);
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if (ret)
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goto out_unwind_iopf;
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domain_remove_dev_pasid(old, dev, pasid);
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return 0;
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out_unwind_iopf:
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iopf_for_domain_replace(old, domain, dev);
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out_remove_dev_pasid:
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domain_remove_dev_pasid(domain, dev, pasid);
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return ret;
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}
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static const struct iommu_domain_ops intel_nested_domain_ops = {
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.attach_dev = intel_nested_attach_dev,
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.set_dev_pasid = intel_nested_set_dev_pasid,
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.free = intel_nested_domain_free,
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.cache_invalidate_user = intel_nested_cache_invalidate_user,
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};
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struct iommu_domain *
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intel_iommu_domain_alloc_nested(struct device *dev, struct iommu_domain *parent,
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u32 flags,
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const struct iommu_user_data *user_data)
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{
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struct device_domain_info *info = dev_iommu_priv_get(dev);
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struct dmar_domain *s2_domain = to_dmar_domain(parent);
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struct intel_iommu *iommu = info->iommu;
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struct iommu_hwpt_vtd_s1 vtd;
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struct dmar_domain *domain;
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int ret;
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if (!nested_supported(iommu) || flags & ~IOMMU_HWPT_ALLOC_PASID)
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return ERR_PTR(-EOPNOTSUPP);
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/* Must be nested domain */
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if (user_data->type != IOMMU_HWPT_DATA_VTD_S1)
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return ERR_PTR(-EOPNOTSUPP);
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if (!intel_domain_is_ss_paging(s2_domain) || !s2_domain->nested_parent)
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return ERR_PTR(-EINVAL);
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ret = iommu_copy_struct_from_user(&vtd, user_data,
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IOMMU_HWPT_DATA_VTD_S1, __reserved);
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if (ret)
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return ERR_PTR(ret);
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domain = kzalloc_obj(*domain, GFP_KERNEL_ACCOUNT);
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if (!domain)
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return ERR_PTR(-ENOMEM);
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domain->s2_domain = s2_domain;
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domain->s1_cfg = vtd;
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domain->domain.ops = &intel_nested_domain_ops;
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domain->domain.type = IOMMU_DOMAIN_NESTED;
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INIT_LIST_HEAD(&domain->devices);
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INIT_LIST_HEAD(&domain->dev_pasids);
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INIT_LIST_HEAD(&domain->cache_tags);
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spin_lock_init(&domain->lock);
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spin_lock_init(&domain->cache_lock);
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xa_init(&domain->iommu_array);
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spin_lock(&s2_domain->s1_lock);
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list_add(&domain->s2_link, &s2_domain->s1_domains);
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spin_unlock(&s2_domain->s1_lock);
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return &domain->domain;
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}
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