mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-10-31 06:14:39 +01:00
Eliot Courtney
5c9deba557
Currently, the frts vidmem offset is calculated based on the non-wpr
heap size and pmu reservation size, but this is not right. The layout
actually looks like this:
| non-wpr heap | WPR2 .. FRTS | PMU reserved | ... | VGA workspace |
It's just by coincidence + generous alignment that the values happened
to match. Instead, define a per-architecture reserved size at the end of
the framebuffer and use this plus the PMU reserved size to calculate the
frts vidmem offset.
Fixes: d317e4585f ("gpu: nova-core: Hopper/Blackwell: add FSP Chain of Trust boot")
Signed-off-by: Eliot Courtney <[email protected]>
Link: https://patch.msgid.link/[email protected]
[acourbot: add comment clarifying reason for testing pmu_reserved_size.]
[acourbot: make fb_end_reserved_size() return u64.]
Signed-off-by: Alexandre Courbot <[email protected]>
37 lines
1.2 KiB
Rust
37 lines
1.2 KiB
Rust
// SPDX-License-Identifier: GPL-2.0
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// SPDX-FileCopyrightText: Copyright (c) 2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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use crate::{
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driver::Bar0,
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gpu::{
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Architecture,
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Chipset, //
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},
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};
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mod gb100;
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mod gb202;
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mod gh100;
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pub(super) trait FspHal {
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/// Returns the secure boot status from the architecture-specific `NV_THERM_I2CS_SCRATCH` register.
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fn fsp_boot_status(&self, bar: Bar0<'_>) -> u32;
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/// Returns the FSP Chain of Trust protocol version this chipset advertises.
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fn cot_version(&self) -> u16;
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// TODO: consider moving this into the TLV firmware metadata when ready
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/// Returns the size reserved at the end of the framebuffer, in bytes.
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fn fb_end_reserved_size(&self) -> u64;
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}
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/// Returns the FSP HAL, or `None` if the architecture doesn't support FSP.
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pub(super) fn fsp_hal(chipset: Chipset) -> Option<&'static dyn FspHal> {
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match chipset.arch() {
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Architecture::Turing | Architecture::Ampere | Architecture::Ada => None,
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Architecture::Hopper => Some(gh100::GH100_HAL),
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Architecture::BlackwellGB10x => Some(gb100::GB100_HAL),
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Architecture::BlackwellGB20x => Some(gb202::GB202_HAL),
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}
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}
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