mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git
synced 2026-10-31 14:23:49 +01:00
Anoop Vijay
a62212b35a
The mailbox PHASE bit in SYSCTRL_MB_CTRL is toggled per-message and
was tracked in software as sc->phase_bit, reset to 0 on error paths.
If the cached value ever drifts from what the hardware last saw, all
following messages carry the wrong phase and get silently misread by
firmware.
Drop the cache and read PHASE directly from SYSCTRL_MB_CTRL before
each frame instead, removing xe_sysctrl_mailbox_init() and its call
sites along with it.
Fixes: 1f95f61818 ("drm/xe/xe_sysctrl: Add System Controller mailbox communication support")
Signed-off-by: Anoop Vijay <[email protected]>
Reviewed-by: Umesh Nerlige Ramappa <[email protected]>
Reviewed-by: Rodrigo Vivi <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Rodrigo Vivi <[email protected]>
(cherry picked from commit 04984fcdbf6876c940c01026a7404c1e9cc91ba7)
Signed-off-by: Rodrigo Vivi <[email protected]>
34 lines
881 B
C
34 lines
881 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2026 Intel Corporation
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*/
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#ifndef _XE_SYSCTRL_MAILBOX_H_
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#define _XE_SYSCTRL_MAILBOX_H_
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#include <linux/bitfield.h>
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#include <linux/types.h>
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#include "abi/xe_sysctrl_abi.h"
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struct xe_sysctrl;
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struct xe_sysctrl_mailbox_command;
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#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
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FIELD_GET(APP_HDR_GROUP_ID_MASK, (hdr)->data)
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#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
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FIELD_GET(APP_HDR_COMMAND_MASK, (hdr)->data)
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#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
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FIELD_GET(APP_HDR_VERSION_MASK, (hdr)->data)
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void xe_sysctrl_create_command(struct xe_sysctrl_mailbox_command *command, u8 group_id, u8 cmd_id,
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void *request, size_t request_len, void *response,
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size_t response_len);
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int xe_sysctrl_send_command(struct xe_sysctrl *sc,
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struct xe_sysctrl_mailbox_command *cmd,
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size_t *rdata_len);
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#endif
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