Geetha sowjanya 6e0aa591af dt-bindings: perf: marvell: Add CN20K DDR PMU binding ...

Marvell CN20K SoCs integrate a DDR Performance Monitoring Unit (PMU)
associated with the DDR controller. The block provides hardware counters
to monitor DDR traffic and performance events and is accessed via a
dedicated MMIO region.

The CN20K DDR PMU is functionally equivalent to the CN10K DDR PMU, with
minor register offset differences.

Signed-off-by: Geetha sowjanya <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Will Deacon <[email protected]>

2026-07-31 15:18:03 +00:00

..

amlogic,g12-ddr-pmu.yaml

…

apm,xgene-pmu.yaml

dt-bindings: perf: Convert apm,xgene-pmu to DT schema

2025-08-15 16:40:12 -05:00

arm,ccn.yaml

…

arm,cmn.yaml

dt-bindings: perf: arm-cmn: Add CMN S3

2024-09-04 16:04:08 +01:00

arm,coresight-pmu.yaml

…

arm,dsu-pmu.yaml

…

arm,ni.yaml

dt-bindings/perf: Add Arm NI-700 PMU

2024-09-06 12:58:28 +01:00

arm,smmu-v3-pmcg.yaml

…

fsl-imx-ddr.yaml

dt-bindings: perf: fsl-imx-ddr: Add compatible string for i.MX8QM, i.MX8QXP and i.MX8DXL

2025-11-24 15:39:05 +00:00

marvell-cn10k-ddr.yaml

dt-bindings: perf: marvell: Add CN20K DDR PMU binding

2026-07-31 15:18:03 +00:00

marvell-cn10k-tad.yaml

…

riscv,pmu.yaml

…

spe-pmu.yaml

…

starfive,jh8100-starlink-pmu.yaml

dt-bindings: perf: starfive: Add JH8100 StarLink PMU

2024-03-04 14:19:48 +00:00