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Stephan Gerhold
4529aababe
Add the qcom,mdm9607-nand compatible for the QPIC NAND controller used inside the MDM9607 SoC. On MDM9607 and other recent SoCs, the QPIC hardware requires 3 clocks (core, aon, ahb). However, access to these clocks is restricted to the RPM firmware that controls the shared power resources for the whole SoC. The clocks cannot be controlled separately, for the OS view of the hardware there is only a single RPM_SMD_QPIC_CLK clock that implicitly enables all of the 3 clocks. The only exception to this are some IPQ* SoC that are not using RPM, there the clocks are directly controlled by the kernel via the clock controller (GCC). Require only one clock in the dt-bindings for MDM9607 to avoid having to define dummy clock entries. Reviewed-by: Krzysztof Kozlowski <[email protected]> Reviewed-by: Manivannan Sadhasivam <[email protected]> Signed-off-by: Stephan Gerhold <[email protected]> Signed-off-by: Miquel Raynal <[email protected]>