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Troy Mitchell
e6b17a690c
The K3 i2s clocks were modelled as a single path behind one MPMU
register:
pll1_d96_25p6 / i2s_153p6_base
`-- i2s_sysclk_src (mux+gate, MPMU_ISCCR)
`-- i2s1_sysclk (DDN, MPMU_ISCCR)
|-- i2s_bclk (div+gate, MPMU_ISCCR)
`-- i2s2_sysclk (mux, parent 0)
The hardware actually has two i2s clock control registers, ISCCR0
(0x0040) and ISCCR1 (0x0044): ISCCR1 drives the common sysclk shared
by i2s0/2/3/4/5 and the common bclk, whose divider always implies a
fixed 1/2 factor in front, while ISCCR0 drives a dedicated path for
i2s1:
pll1_d96_25p6 / i2s_153p6_base
|-- i2s_sysclk_src (mux+gate, MPMU_ISCCR1)
| `-- i2s_sysclk (DDN, MPMU_ISCCR1)
| |-- i2s_bclk_factor (fixed factor, /2)
| | `-- i2s_bclk (div+gate, MPMU_ISCCR1)
| `-- i2s2_sysclk (mux, parent 0)
`-- i2s1_sysclk_src (mux+gate, MPMU_ISCCR0)
`-- i2s1_sysclk (DDN, MPMU_ISCCR0)
Because of this mismatch, i2s_bclk reported twice the real rate, and
the dedicated i2s1 clock path could not be described in DT at all.
Model the tree as above: split the MPMU_ISCCR register macro into
MPMU_ISCCR0 and MPMU_ISCCR1 to match the hardware register names,
rename the common DDN to i2s_sysclk, insert the fixed 1/2 factor
i2s_bclk_factor in front of i2s_bclk, and add the i2s1_sysclk_src mux
and i2s1_sysclk DDN backed by MPMU_ISCCR0. CLK_MPMU_I2S1_SYSCLK now
refers to the dedicated i2s1 clock; no in-tree user references this
ID, so nothing is affected by the change of meaning.
Fixes: e371a77255 ("clk: spacemit: k3: add the clock tree")
Signed-off-by: Troy Mitchell <[email protected]>
Reviewed-by: Yixun Lan <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Yixun Lan <[email protected]>