Commit Graph
5259 Commits
Author SHA1 Message Date
Bjorn Andersson 62209e805b pinctrl: qcom: sm8350: Correct UFS and SDC offsets
The downstream TLMM binding covers a group of TLMM-related hardware
blocks, but the upstream binding only captures the particular block
related to controlling the TLMM pins from an OS. In the translation of
the driver from downstream, the offset of 0x100000 was lost for the UFS
and SDC pingroups.

Fixes: d5d348a327 ("pinctrl: qcom: Add SM8350 pinctrl driver")
Signed-off-by: Bjorn Andersson <[email protected]>
Reviewed-by: Vinod Koul <[email protected]>
Reviewed-by: Vladimir Zapolskiy <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:15 +01:00
Arnd Bergmann 293083f877 pinctrl: tegra194: remove duplicate initializer again
An earlier bugfix removed a duplicate field initializer in
a macro, but it seems that this came back with the following
update:

drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: error: initialized field overwritten [-Werror=override-init]
 1341 |                 .drv_reg = ((r)),                               \
      |                            ^
drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y'
 1392 | #define drive_touch_clk_pcc4            DRV_PINGROUP_ENTRY_Y(0x2004,    12,     5,      20,     5,      -1,     -1,     -1,     -1,     1)
      |                                         ^~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4'
 1631 |                 drive_##pg_name,                                \
      |                 ^~~~~~
drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP'
 1636 |         PINGROUP(touch_clk_pcc4,        GP,             TOUCH,          RSVD2,          RSVD3,          0x2000,         1,      Y,      -1,     -1,     6,      8,      -1,     10,     11,     12,     N,      -1,     -1,     N,      "vddio_ao"),
      |         ^~~~~~~~
drivers/pinctrl/tegra/pinctrl-tegra194.c:1341:28: note: (near initialization for 'tegra194_groups[0].drv_reg')
 1341 |                 .drv_reg = ((r)),                               \
      |                            ^
drivers/pinctrl/tegra/pinctrl-tegra194.c:1392:41: note: in expansion of macro 'DRV_PINGROUP_ENTRY_Y'
 1392 | #define drive_touch_clk_pcc4            DRV_PINGROUP_ENTRY_Y(0x2004,    12,     5,      20,     5,      -1,     -1,     -1,     -1,     1)
      |                                         ^~~~~~~~~~~~~~~~~~~~
drivers/pinctrl/tegra/pinctrl-tegra194.c:1631:17: note: in expansion of macro 'drive_touch_clk_pcc4'
 1631 |                 drive_##pg_name,                                \
      |                 ^~~~~~
drivers/pinctrl/tegra/pinctrl-tegra194.c:1636:9: note: in expansion of macro 'PINGROUP'
 1636 |         PINGROUP(touch_clk_pcc4,        GP,             TOUCH,          RSVD2,          RSVD3,          0x2000,         1,      Y,      -1,     -1,     6,      8,      -1,     10,     11,     12,     N,      -1,     -1,     N,      "vddio_ao"),
      |         ^~~~~~~~

Remove it again.

Fixes: 613c082608 ("pinctrl: tegra: Add pinmux support for Tegra194")
Fixes: 92cadf68e5 ("pinctrl: tegra: pinctrl-tegra194: Do not initialise field twice")
Signed-off-by: Arnd Bergmann <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:15 +01:00
Bjorn Andersson 3a3a100473 pinctrl: qcom: sdm845: Enable dual edge errata
It has been observed that dual edge triggered wakeirq GPIOs on SDM845
doesn't trigger interrupts on the falling edge.

Enabling wakeirq_dual_edge_errata for SDM845 indicates that the PDC in
SDM845 suffers from the same problem described, and worked around, by
Doug in 'c3c0c2e18d94 ("pinctrl: qcom: Handle broken/missing PDC dual
edge IRQs on sc7180")', so enable the workaround for SDM845 as well.

The specific problem seen without this is that gpio-keys does not detect
the falling edge of the LID gpio on the Lenovo Yoga C630 and as such
consistently reports the LID as closed.

Fixes: e35a6ae0eb ("pinctrl/msm: Setup GPIO chip in hierarchy")
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-By: Steev Klimaszewski <[email protected]>
Reviewed-by: Douglas Anderson <[email protected]>
Reviewed-by: Stephen Boyd <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:15 +01:00
Sven Peter 9b3b94e9eb pinctrl: apple: Always return valid type in apple_gpio_irq_type
apple_gpio_irq_type can possibly return -EINVAL which triggers the
following compile error with gcc 9 because the type no longer fits
into the mask.

  drivers/pinctrl/pinctrl-apple-gpio.c: In function 'apple_gpio_irq_set_type':
  ././include/linux/compiler_types.h:335:38: error: call to '__compiletime_assert_289' declared with attribute error: FIELD_PREP: value too large for the field
    335 |  _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
        |                                      ^
  [...]
  drivers/pinctrl/pinctrl-apple-gpio.c:294:7: note: in expansion of macro 'FIELD_PREP'
    294 |       FIELD_PREP(REG_GPIOx_MODE, irqtype));
        |       ^~~~~~~~~~

Fix this by making the return value always valid and instead checking
for REG_GPIOx_IN_IRQ_OFF in apple_gpio_irq_set_type and return -EINVAL
from there.

Fixes: a0f160ffcb ("pinctrl: add pinctrl/GPIO driver for Apple SoCs")
Signed-off-by: Sven Peter <[email protected]>
Reviewed-by: Joey Gouly <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:15 +01:00
Sergio Paracuellos a5b9703fe1 pinctrl: ralink: include 'ralink_regs.h' in 'pinctrl-mt7620.c'
mt7620.h, included by pinctrl-mt7620.c, mentions MT762X_SOC_MT7628AN
declared in ralink_regs.h.

Fixes: 745ec436de ("pinctrl: ralink: move MT7620 SoC pinmux config into a new 'pinctrl-mt7620.c' file")
Cc: [email protected]
Signed-off-by: Luiz Angelo Daros de Luca <[email protected]>
Signed-off-by: Sergio Paracuellos <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:14 +01:00
Julian Braha 60430d4c4e pinctrl: qcom: fix unmet dependencies on GPIOLIB for GPIOLIB_IRQCHIP
When PINCTRL_QCOM_SPMI_PMIC or PINCTRL_QCOM_SSBI_PMIC
is selected, and GPIOLIB is not selected, Kbuild
gives the following warnings:

WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP
  Depends on [n]: GPIOLIB [=n]
  Selected by [y]:
  - PINCTRL_QCOM_SPMI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y] && SPMI [=y]

WARNING: unmet direct dependencies detected for GPIOLIB_IRQCHIP
  Depends on [n]: GPIOLIB [=n]
  Selected by [y]:
  - PINCTRL_QCOM_SSBI_PMIC [=y] && PINCTRL [=y] && (ARCH_QCOM [=n] || COMPILE_TEST [=y]) && OF [=y]

This is because these config options enable GPIOLIB_IRQCHIP
without selecting or depending on GPIOLIB, despite
GPIOLIB_IRQCHIP depending on GPIOLIB.

These unmet dependency bugs were detected by Kismet,
a static analysis tool for Kconfig. Please advise if this
is not the appropriate solution.

Signed-off-by: Julian Braha <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:14 +01:00
Prathamesh Shete 55924812d2 pinctrl: tegra: Return const pointer from tegra_pinctrl_get_group()
Instead of returning const pointer from tegra_pinctrl_get_group()
the return value is being casted.

This change helps return const pointer.

Signed-off-by: Prathamesh Shete <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:14 +01:00
Mario Limonciello 2d54067fcd pinctrl: amd: Fix wakeups when IRQ is shared with SCI
On some Lenovo AMD Gen2 platforms the IRQ for the SCI and pinctrl drivers
are shared.  Due to how the s2idle loop handling works, this case needs
an extra explicit check whether the interrupt was caused by SCI or by
the GPIO controller.

To fix this rework the existing IRQ handler function to function as a
checker and an IRQ handler depending on the calling arguments.

BugLink: https://gitlab.freedesktop.org/drm/amd/-/issues/1738
Reported-by: Joerie de Gram <[email protected]>
Signed-off-by: Mario Limonciello <[email protected]>
Acked-by: Basavaraj Natikar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-11-16 02:19:14 +01:00
Linus Torvalds 5a1bcbd965 Merge tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pin control updates from Linus Walleij:
 "The most interesting aspect is that we now have initial support for
  the Apple pin controller as used in the M1 laptops and the iPhones
  which is a step forward for using Linux efficiently on this Apple
  silicon.

  Core changes:

   - Add infrastructure for per-parent interrupt data to support the
     Apple pin controller.

  New drivers:

   - New combined pin control and GPIO driver for the Apple SoC. This is
     used in all modern Apple silicon such as the M1 laptops but also in
     at least recent iPhone variants.

   - New subdriver for the Qualcomm SM6350

   - New subdriver for the Qualcomm QCM2290

   - New subdriver for the Qualcomm PM6350

   - New subdriver for the Uniphier NX1

   - New subdriver for the Samsung ExynosAutoV9

   - New subdriver for the Mediatek MT7986

   - New subdriver for the nVidia Tegra194

  Improvements:

   - Improve power management in the Mediatek driver.

   - Improvements to the Renesas internal consistency checker.

   - Convert the Rockchip pin control device tree bindings to YAML.

   - Finally convert the Qualcomm PMIC SSBI and SPMI MPP GPIO driver to
     use hierarchical interrupts.

   - Convert the Qualcomm PMIC MPP device tree bindings to YAML"

* tag 'pinctrl-v5.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (55 commits)
  pinctrl: add pinctrl/GPIO driver for Apple SoCs
  dt-bindings: pinctrl: Add apple,npins property to apple,pinctrl
  dt-bindings: pinctrl: add #interrupt-cells to apple,pinctrl
  gpio: Allow per-parent interrupt data
  pinctrl: tegra: Fix warnings and error
  pinctrl: intel: Kconfig: Add configuration menu to Intel pin control
  pinctrl: tegra: Use correct offset for pin group
  pinctrl: core: fix possible memory leak in pinctrl_enable()
  pinctrl: bcm2835: Allow building driver as a module
  pinctrl: equilibrium: Fix function addition in multiple groups
  pinctrl: tegra: Add pinmux support for Tegra194
  pinctrl: tegra: include lpdr pin properties
  pinctrl: mediatek: add support for MT7986 SoC
  dt-bindings: pinctrl: update bindings for MT7986 SoC
  pinctrl: microchip sgpio: use reset driver
  dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add reset binding
  dt-bindings: pinctrl: qcom,pmic-mpp: switch to #interrupt-cells
  pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip
  pinctrl: qcom: spmi-mpp: hardcode IRQ counts
  pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip
  ...
2021-11-05 08:24:17 -07:00
Joey Gouly a0f160ffcb pinctrl: add pinctrl/GPIO driver for Apple SoCs
This driver adds support for the pinctrl / GPIO hardware found
on some Apple SoCs.

Co-developed-by: Stan Skowronek <[email protected]>
Signed-off-by: Stan Skowronek <[email protected]>
Signed-off-by: Joey Gouly <[email protected]>
Acked-by: Hector Martin <[email protected]>
Reviewed-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-27 00:16:52 +02:00
Prathamesh Shete f0c142fcf4 pinctrl: tegra: Fix warnings and error
Fix warnings are errors caused by commit a42c7d95d2
("pinctrl: tegra: Use correct offset for pin group").

Signed-off-by: Prathamesh Shete <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
2021-10-26 19:59:44 +02:00
Cai Huoqing d238817238 pinctrl: intel: Kconfig: Add configuration menu to Intel pin control
Adding a configuration menu to hold many Intel pin control drivers
helps to make the display more concise.

Acked-by: Andy Shevchenko <[email protected]>
Signed-off-by: Cai Huoqing <[email protected]>
Signed-off-by: Mika Westerberg <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
2021-10-26 01:30:11 +02:00
Prathamesh Shete a42c7d95d2 pinctrl: tegra: Use correct offset for pin group
Function tegra_pinctrl_gpio_request_enable() and
tegra_pinctrl_gpio_disable_free() uses pin offset instead
of group offset, causing the driver to use wrong offset
to enable gpio.

Add a helper function tegra_pinctrl_get_group() to parse the
pin group and determine correct offset.

Signed-off-by: Kartik K <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-26 01:27:39 +02:00
Yang Yingliang c7892ae13e pinctrl: core: fix possible memory leak in pinctrl_enable()
I got memory leak as follows when doing fault injection test:

unreferenced object 0xffff888020a7a680 (size 64):
  comm "i2c-mcp23018-41", pid 23090, jiffies 4295160544 (age 8.680s)
  hex dump (first 32 bytes):
    00 48 d3 1e 80 88 ff ff 00 1a 56 c1 ff ff ff ff  .H........V.....
    00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00  ................
  backtrace:
    [<0000000083c79b35>] kmem_cache_alloc_trace+0x16d/0x360
    [<0000000051803c95>] pinctrl_init_controller+0x6ed/0xb70
    [<0000000064346707>] pinctrl_register+0x27/0x80
    [<0000000029b0e186>] devm_pinctrl_register+0x5b/0xe0
    [<00000000391f5a3e>] mcp23s08_probe_one+0x968/0x118a [pinctrl_mcp23s08]
    [<000000006112c039>] mcp230xx_probe+0x266/0x560 [pinctrl_mcp23s08_i2c]

If pinctrl_claim_hogs() fails, the 'pindesc' allocated in pinctrl_register_one_pin()
need be freed.

Cc: [email protected]
Reported-by: Hulk Robot <[email protected]>
Fixes: 950b0d91dc ("pinctrl: core: Fix regression caused by delayed work for hogs")
Signed-off-by: Yang Yingliang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-25 01:43:43 +02:00
Florian Fainelli 4434f4c503 pinctrl: bcm2835: Allow building driver as a module
Update the pinctrl-bcm2835 driver to support being built as as a module
by converting it to a module_platform_driver() with the appropriate
module license, authors and description.

Signed-off-by: Florian Fainelli <[email protected]>
Reviewed-by: Nicolas Saenz Julienne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-25 00:54:21 +02:00
Rahul Tanwar 53b3947ddb pinctrl: equilibrium: Fix function addition in multiple groups
Ignore the same function with multiple groups.
Fix a typo in error print.

Fixes: 1948d5c51d ("pinctrl: Add pinmux & GPIO controller driver for a new SoC")
Signed-off-by: Rahul Tanwar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-25 00:20:01 +02:00
Prathamesh Shete 613c082608 pinctrl: tegra: Add pinmux support for Tegra194
This change adds pinmux table entries for Tegra194

Signed-off-by: Prathamesh Shete <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-24 23:14:48 +02:00
Suresh Mangipudi 8d886bba3b pinctrl: tegra: include lpdr pin properties
Update lpdr pin-property for supported pins.

lpdr property help disable most basic driver fingers
leaving only minimal base driver finger.

Signed-off-by: Suresh Mangipudi <[email protected]>
Signed-off-by: Prathamesh Shete <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-24 23:14:48 +02:00
Sam Shih 360de67280 pinctrl: mediatek: add support for MT7986 SoC
This commit includes pinctrl driver for Mediatek MT7986

The difference of pinctrl between mt7986a and mt7986b
is that pin-41 to pin-65 do not exist on mt7986b

Signed-off-by: Sam Shih <[email protected]>
Acked-by: Sean Wang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-24 23:06:32 +02:00
Horatiu Vultur 0b90315af7 pinctrl: microchip sgpio: use reset driver
On lan966x platform when the switch gets reseted then also the sgpio
gets reseted. The fix for this is to extend also the sgpio driver to
call the reset driver which will be reseted only once by the first
driver that is probed.

Signed-off-by: Horatiu Vultur <[email protected]>
Reviewed-by: Steen Hegelund <[email protected]>
Reviewed-by: Philipp Zabel <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-24 23:03:26 +02:00
Dmitry Baryshkov afe6777f2e pinctrl: qcom: spmi-mpp: add support for hierarchical IRQ chip
spmi-mpp did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should be
usable from the start without the consumer having to make an additional
call to get the proper IRQ on the parent. This patch adds hierarchical
IRQ chip support to the spmi-mpp code to correct this issue.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-17 23:32:46 +02:00
Dmitry Baryshkov f24dbaaab4 pinctrl: qcom: spmi-mpp: hardcode IRQ counts
The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process.

This change will also allow for the removal of the interrupts property
later in this patch series once the hierarchical IRQ chip support is in.

This patch also removes the generic qcom,spmi-mpp OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-17 23:32:33 +02:00
Dmitry Baryshkov 56b2443fb4 pinctrl: qcom: ssbi-mpp: add support for hierarchical IRQ chip
ssbi-mpp did not have any irqchip support so consumers of this in
device tree would need to call gpio[d]_to_irq() in order to get the
proper IRQ on the underlying PMIC. IRQ chips in device tree should be
usable from the start without the consumer having to make an additional
call to get the proper IRQ on the parent. This patch adds hierarchical
IRQ chip support to the ssbi-mpp code to correct this issue.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-17 23:32:20 +02:00
Dmitry Baryshkov 461030b804 pinctrl: qcom: ssbi-mpp: hardcode IRQ counts
The probing of this driver calls platform_irq_count, which will
setup all of the IRQs that are configured in device tree. In
preparation for converting this driver to be a hierarchical IRQ
chip, hardcode the IRQ count based on the hardware type so that all
the IRQs are not configured immediately and are configured on an
as-needed basis later in the boot process.

This change will also allow for the removal of the interrupts property
later in this patch series once the hierarchical IRQ chip support is in.

This patch also removes the generic qcom,ssbi-mpp OF match since we
don't know the number of pins. All of the existing upstream bindings
already include the more-specific binding.

Signed-off-by: Dmitry Baryshkov <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-17 23:31:59 +02:00
Chanho Park 02725b0c89 pinctrl: samsung: support ExynosAutov9 SoC pinctrl
Add pinctrl data for ExynosAuto v9 SoC.

- GPA0, GPA1: 10, External wake up interrupt
- GPQ0: 2, XbootLDO, Speedy PMIC I/F
- GPB0, GPB1, GPB2, GPB3: 29, I2S 7 CH
- GPF0, GPF1, GPF2, GPF3,GPF4, GPF5, GPF6, GPF8: 52, FSYS
- GPG0, GPG1, GPG2, GPG3: 25, GPIO x 24, SMPL_INT
- GPP0, GPP1, GPP2, GPP3, GPP4, GPP5: 48, USI 12 CH

Signed-off-by: Chanho Park <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-17 23:24:33 +02:00
Linus Walleij 57135c2810 Merge tag 'renesas-pinctrl-for-v5.16-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.16 (take two)

  - Add MediaLB pins on R-Car H3, M3-W/W+, and M3-N.
  - Miscellaneous fixes and improvements.
2021-10-17 00:06:50 +02:00
Sachi King 4e5a04be88 pinctrl: amd: disable and mask interrupts on probe
Some systems such as the Microsoft Surface Laptop 4 leave interrupts
enabled and configured for use in sleep states on boot, which cause
unexpected behaviour such as spurious wakes and failed resumes in
s2idle states.

As interrupts should not be enabled until they are claimed and
explicitly enabled, disabling any interrupts mistakenly left enabled by
firmware should be safe.

Signed-off-by: Sachi King <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-16 23:56:59 +02:00
Geert Uytterhoeven f4e260bffc pinctrl: renesas: checker: Prefix common checker output
Add a "sh_pfc: " prefix to common checker output that is not yet
prefixed by a subdriver-specific prefix ("<SoC-part-number>_pfc: "), for
easier grepping.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/9cf1dc9f895dc5fa74125dabddfe46fecf438b4f.1633615652.git.geert+renesas@glider.be
2021-10-15 09:48:00 +02:00
Geert Uytterhoeven f31a5ffbd1 pinctrl: renesas: checker: Fix bias checks on SoCs with pull-down only pins
If some bits in a pin Pull-Up control register (PUPR) control pin
pull-down instead of pin pull-up, there are two pinmux_bias_reg entries:
a first one with the puen field filled in, listing pins with pull-up
functionality, and a second one with the pud field filled in, listing
pins with pull-down functionality.  On encountering the second entry,
where puen is NULL, the for-loop terminates early, causing the remaining
bias registers not to be checked.  In addition, sh_pfc_check_bias_reg()
does not handle such entries.

Fix this by treating pinmux_bias_reg.puen and pinmux_bias_reg.pud the
same.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/29526d06fa223cffd785cdb264b756a202b11cea.1633615652.git.geert+renesas@glider.be
2021-10-15 09:48:00 +02:00
Geert Uytterhoeven e212923e74 pinctrl: renesas: checker: Move overlapping field check
Move the check for overlapping drive register fields from
sh_pfc_check_drive_reg() to sh_pfc_check_reg(), so it can be used for
other register types, too.  This requires passing the covered register
bits to sh_pfc_check_reg().

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/9d75057200890bbf31e226ffcc4514ecc5bc2c34.1633615652.git.geert+renesas@glider.be
2021-10-15 09:48:00 +02:00
Geert Uytterhoeven 28e7f8ff90 pinctrl: renesas: checker: Fix off-by-one bug in drive register check
The GENMASK(h, l) macro creates a contiguous bitmask starting at bit
position @l and ending at position @h, inclusive.

This did not trigger any error checks, as the individual register fields
cover at most 3 of the 4 available bits.

Fixes: 08df16e07a ("pinctrl: sh-pfc: checker: Add drive strength register checks")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/8f82d6147fbe3367d4c83962480e97f58d9c96a2.1633615652.git.geert+renesas@glider.be
2021-10-15 09:48:00 +02:00
Geert Uytterhoeven 412da8c722 pinctrl: renesas: Fix save/restore on SoCs with pull-down only pins
If some bits in a pin Pull-Up control register (PUPR) control pin
pull-down instead of pin pull-up, there are two pinmux_bias_reg entries:
a first one with the puen field filled in, listing pins with pull-up
functionality, and a second one with the pud field filled in, listing
pins with pull-down functionality.  On encountering the second entry,
where puen is NULL, the for-loop terminates early, causing the remaining
bias registers not to be saved/restored during PSCI system suspend.
Fortunately this does not trigger on any supported system yet, as PSCI
is only used on R-Car Gen3 and RZ/G2 systems, which all have separate
pin Pull-Enable (PUEN) and pin Pull-Up/Down control (PUD) registers.

Avoid this ever becoming a problem by treating pinmux_bias_reg.puen and
pinmux_bias_reg.pud the same.  Note that a register controlling both
pull-up and pull-down pins would be saved and restored twice, which is
harmless.

Signed-off-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/r/59d2fbddff685b6a7a82ff17d2b37633e30e8860.1633615652.git.geert+renesas@glider.be
2021-10-15 09:48:00 +02:00
Andrey Gusakov ce34fb3cb4 pinctrl: renesas: r8a779[56]x: Add MediaLB pins
This adds pins, groups, and functions for MediaLB devices on Renesas
R-Car H3 and M3-W/N SoCs.

Signed-off-by: Andrey Gusakov <[email protected]>
Signed-off-by: Vladimir Barinov <[email protected]>
Signed-off-by: LUU HOAI <[email protected]>
Signed-off-by: Nikita Yushchenko <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[geert: Fix automotive handling]
Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-10-15 09:47:53 +02:00
Du Huanpeng c30174d333 pinctrl: gemini: fix typos
Signed-off-by: Du Huanpeng <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-14 01:22:58 +02:00
Fabien Dessenne c370bb4740 pinctrl: stm32: use valid pin identifier in stm32_pinctrl_resume()
When resuming from low power, the driver attempts to restore the
configuration of some pins. This is done by a call to:
  stm32_pinctrl_restore_gpio_regs(struct stm32_pinctrl *pctl, u32 pin)
where 'pin' must be a valid pin value (i.e. matching some 'groups->pin').
Fix the current implementation which uses some wrong 'pin' value.

Fixes: e2f3cf18c3 ("pinctrl: stm32: add suspend/resume management")
Signed-off-by: Fabien Dessenne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-14 01:16:12 +02:00
Fabien Dessenne 576ad176ad pinctrl: stm32: do not warn when 'st,package' is absent
Since the 'st,package' property is optional, outputting the "No package
detected" warning-level log when the property is absent is unsuitable.
Remove that log.

Signed-off-by: Fabien Dessenne <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-14 01:14:58 +02:00
Rafał Miłecki 6dba4bdfd7 Revert "pinctrl: bcm: ns: support updated DT binding as syscon subnode"
This reverts commit a49d784d5a.

The updated binding was wrong / invalid and has been reverted. There
isn't any upstream kernel DTS using it and Broadcom isn't known to use
it neither. There is close to zero chance this will cause regression for
anyone.

Actually in-kernel bcm5301x.dtsi still uses the old good binding and so
it's broken since the driver update. This revert fixes it.

Signed-off-by: Rafał Miłecki <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-14 01:09:07 +02:00
Kunihiko Hayashi b0b2303c02 pinctrl: uniphier: Add UniPhier NX1 pinctrl driver
Add pin configuration and pinmux support for UniPhier NX1 SoC.

Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Kunihiko Hayashi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-13 02:13:47 +02:00
Kunihiko Hayashi 290e2d18ca pinctrl: uniphier: Add extra audio pinmux settings for LD11, LD20 and PXs3 SoCs
Add extra audio I/O pinmux setting for LD11, LD20 and PXs3 SoCs.

Signed-off-by: Kunihiko Hayashi <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-13 02:13:47 +02:00
Luca Weiss 8391785633 pinctrl: qcom: spmi-gpio: Add compatible for PM6350
Add support for the GPIO controller in the pm6350 PMIC.

Signed-off-by: Luca Weiss <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-13 01:48:34 +02:00
Linus Torvalds 0dcf60d001 Merge tag 'asm-generic-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic
Pull asm-generic fixes from Arnd Bergmann:
 "There is one build fix for Arm platforms that ended up impacting most
  architectures because of the way the drivers/firmware Kconfig file is
  wired up:

  The CONFIG_QCOM_SCM dependency have caused a number of randconfig
  regressions over time, and some still remain in v5.15-rc4. The fix we
  agreed on in the end is to make this symbol selected by any driver
  using it, and then building it even for non-Arm platforms with
  CONFIG_COMPILE_TEST.

  To make this work on all architectures, the drivers/firmware/Kconfig
  file needs to be included for all architectures to make the symbol
  itself visible.

  In a separate discussion, we found that a sound driver patch that is
  pending for v5.16 needs the same change to include this Kconfig file,
  so the easiest solution seems to have my Kconfig rework included in
  v5.15.

  Finally, the branch also includes a small unrelated build fix for
  NOMMU architectures"

Link: https://lore.kernel.org/all/[email protected]/
Link: https://lore.kernel.org/all/[email protected]/
Link: https://lore.kernel.org/all/[email protected]/

* tag 'asm-generic-fixes-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
  asm-generic/io.h: give stub iounmap() on !MMU same prototype as elsewhere
  qcom_scm: hide Kconfig symbol
  firmware: include drivers/firmware/Kconfig unconditionally
2021-10-08 11:57:54 -07:00
Arnd Bergmann 424953cf3c qcom_scm: hide Kconfig symbol
Now that SCM can be a loadable module, we have to add another
dependency to avoid link failures when ipa or adreno-gpu are
built-in:

aarch64-linux-ld: drivers/net/ipa/ipa_main.o: in function `ipa_probe':
ipa_main.c:(.text+0xfc4): undefined reference to `qcom_scm_is_available'

ld.lld: error: undefined symbol: qcom_scm_is_available
>>> referenced by adreno_gpu.c
>>>               gpu/drm/msm/adreno/adreno_gpu.o:(adreno_zap_shader_load) in archive drivers/built-in.a

This can happen when CONFIG_ARCH_QCOM is disabled and we don't select
QCOM_MDT_LOADER, but some other module selects QCOM_SCM. Ideally we'd
use a similar dependency here to what we have for QCOM_RPROC_COMMON,
but that causes dependency loops from other things selecting QCOM_SCM.

This appears to be an endless problem, so try something different this
time:

 - CONFIG_QCOM_SCM becomes a hidden symbol that nothing 'depends on'
   but that is simply selected by all of its users

 - All the stubs in include/linux/qcom_scm.h can go away

 - arm-smccc.h needs to provide a stub for __arm_smccc_smc() to
   allow compile-testing QCOM_SCM on all architectures.

 - To avoid a circular dependency chain involving RESET_CONTROLLER
   and PINCTRL_SUNXI, drop the 'select RESET_CONTROLLER' statement.
   According to my testing this still builds fine, and the QCOM
   platform selects this symbol already.

Acked-by: Kalle Valo <[email protected]>
Acked-by: Alex Elder <[email protected]>
Signed-off-by: Arnd Bergmann <[email protected]>
2021-10-07 16:51:57 +02:00
Linus Walleij 5077a3240b Merge tag 'renesas-pinctrl-for-v5.16-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
pinctrl: renesas: Updates for v5.16

  - Fix duplicate port register on RZ/G2L,
  - A minor improvement.
2021-10-03 23:47:25 +02:00
Zhiyong Tao 387292c357 pinctrl: mediatek: add rsel setting on MT8195
I2C pins's resistance value can be controlled by rsel register.
This patch provides rsel (resistance selection) setting on MT8195

Signed-off-by: Zhiyong Tao <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-03 00:43:36 +02:00
Zhiyong Tao fb34a9ae38 pinctrl: mediatek: support rsel feature
This patch supports rsel(resistance selection) feature for I2C pins.
It provides more resistance selection solution in different ICs.
It provides rsel define and si unit solution by identifying
"mediatek,rsel_resistance_in_si_unit" property in pio dtsi node.

Signed-off-by: Zhiyong Tao <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-03 00:43:36 +02:00
Zhiyong Tao 25a74c0f4b pinctrl: mediatek: fix coding style
Fix Camel spelling coding style to avoid checkpatch
warning in a following patch.

Signed-off-by: Zhiyong Tao <[email protected]>
Reviewed-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-03 00:43:36 +02:00
Subbaraman Narayanamurthy 727293a8b1 pinctrl: qcom: spmi-gpio: add support to enable/disable output
Currently, if the GPIO is configured as output in the bootloader
and user changes the mode to input in HLOS, it would end up
getting configured as input/output. Functionally, this is fine;
however, there may be some requirements where the output needs
to be disabled so that it can be used only for input.

Add support to enable/disable output mode through "output-enable"
or "output-disable" pinctrl properties.

Signed-off-by: Subbaraman Narayanamurthy <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[Drop copyright change which is already upstrean in -rcN]
Signed-off-by: Linus Walleij <[email protected]>
2021-10-03 00:43:09 +02:00
Biju Das fcfb63148c pinctrl: renesas: rzg2l: Fix missing port register 21h
Remove the duplicate port register 22h and replace it with missing port
register 21h.

Signed-off-by: Biju Das <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Fixes: c4c4637eb5 ("pinctrl: renesas: Add RZ/G2L pin and gpio controller driver")
Signed-off-by: Geert Uytterhoeven <[email protected]>
2021-09-24 15:14:49 +02:00
Shawn Guo 48e049ef12 pinctrl: qcom: Add QCM2290 pinctrl driver
It's a porting of pinctrl-scuba driver from CAF msm-4.19 kernel.  The
egpio and wake bits are removed.

Signed-off-by: Shawn Guo <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-09-23 23:13:24 +02:00
Konrad Dybcio 7d74b55afd pinctrl: qcom: Add SM6350 pinctrl driver
This adds pincontrol driver for tlmm block found in SM6350 SoC

This patch is based on downstream copyleft code.

Reviewed-by: AngeloGioacchino Del Regno <[email protected]>
Signed-off-by: Konrad Dybcio <[email protected]>
Reviewed-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Linus Walleij <[email protected]>
2021-09-23 23:10:41 +02:00