Pull pwm updates from Thierry Reding:
"The majority of this batch is conversion of the PWM period and duty
cycle to 64-bit unsigned integers, which is required so that some
types of hardware can generate the full range of signals that they're
capable of.
The remainder is mostly minor fixes and cleanups"
* tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm:
pwm: bcm-iproc: handle clk_get_rate() return
pwm: Replace HTTP links with HTTPS ones
pwm: omap-dmtimer: Repair pwm_omap_dmtimer_chip's broken kerneldoc header
pwm: mediatek: Provide missing kerneldoc description for 'soc' arg
pwm: bcm-kona: Remove impossible comparison when validating duty cycle
pwm: bcm-iproc: Remove impossible comparison when validating duty cycle
pwm: iqs620a: Use lowercase hexadecimal literals for consistency
pwm: Convert period and duty cycle to u64
clk: pwm: Use 64-bit division function
backlight: pwm_bl: Use 64-bit division function
pwm: sun4i: Use nsecs_to_jiffies to avoid a division
pwm: sifive: Use 64-bit division macro
pwm: iqs620a: Use 64-bit division
pwm: imx27: Use 64-bit division macro
pwm: imx-tpm: Use 64-bit division macro
pwm: clps711x: Use 64-bit division macro
hwmon: pwm-fan: Use 64-bit division macro
drm/i915: Use 64-bit division macro
Rationale:
Reduces attack surface on kernel devs opening the links for MITM
as HTTPS traffic is much harder to manipulate.
Deterministic algorithm:
For each file:
If not .svg:
For each line:
If doesn't contain `\bxmlns\b`:
For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`:
If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`:
If both the HTTP and HTTPS versions
return 200 OK and serve the same content:
Replace HTTP with HTTPS.
Signed-off-by: Alexander A. Klimov <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Argument descriptions must be prepended with a '@' to be understood
by the kerneldoc tooling/parsers/validators.
Fixes the following W=1 warning:
drivers/pwm/pwm-omap-dmtimer.c:70: warning: Function parameter or member 'dm_timer_pdev' not described in 'pwm_omap_dmtimer_chip'
Cc: Tony Lindgren <[email protected]>
Cc: Joachim Eastwood <[email protected]>
Cc: NeilBrown <[email protected]>
Cc: Grant Erickson <[email protected]>
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
'dc' here is an unsigned long, thus checking for <0 will always
evaluate to false.
Fixes the following W=1 warning:
drivers/pwm/pwm-bcm-kona.c:141:35: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
Cc: Florian Fainelli <[email protected]>
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
'duty' here is an unsigned int, thus checking for <0 will always
evaluate to false.
Fixes the following W=1 warning:
drivers/pwm/pwm-bcm-iproc.c:147:12: warning: comparison of unsigned expression < 0 is always false [-Wtype-limits]
Cc: Ray Jui <[email protected]>
Cc: Scott Branden <[email protected]>
Cc: Yendapally Reddy Dhananjaya Reddy <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Lee Jones <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The unicore32 port is removed from the kernel.
There is no point to keep stale PWM driver for this architecture.
Signed-off-by: Mike Rapoport <[email protected]>
Acked-by: Arnd Bergmann <[email protected]>
Acked-by: Guenter Roeck <[email protected]>
Other drivers use lowercase hexadecimal literals, so convert the IQS620a
driver to do the same for consistency.
Signed-off-by: Thierry Reding <[email protected]>
Because period and duty cycle are defined as ints with units of
nanoseconds, the maximum time duration that can be set is limited to
~2.147 seconds. Change their definitions to u64 in the structs of the
PWM framework so that higher durations may be set.
Also use the right format specifiers in debug prints in both core.c,
pwm-stm32-lp.c as well as video/fbdev/ssd1307fb.c.
Reported-by: kbuild test robot <[email protected]>
Signed-off-by: Guru Das Srinagesh <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Since the PWM framework is switching struct pwm_state.period's datatype
to u64, prepare for this transition by using nsecs_to_jiffies() which
does away with the need for a division operation.
Signed-off-by: Guru Das Srinagesh <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Since the PWM framework is switching struct pwm_args.period's datatype
to u64, prepare for this transition by using DIV64_U64_ROUND_CLOSEST to
handle a 64-bit divisor.
Signed-off-by: Guru Das Srinagesh <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The PWM framework is going to change the PWM period and duty cycles to
be 64-bit unsigned integers. To avoid build errors on platforms that do
not natively support 64-bit division, use explicity 64-bit division.
Acked-by: Uwe Kleine-König <[email protected]>
Acked-by: Lee Jones <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Since the PWM framework is switching struct pwm_state.period's
datatype to u64, prepare for this transition by using
DIV_ROUND_UP_ULL to handle a 64-bit dividend.
Signed-off-by: Guru Das Srinagesh <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Since the PWM framework is switching struct pwm_args.period's datatype
to u64, prepare for this transition by using DIV64_U64_ROUND_CLOSEST to
handle a 64-bit divisor.
Cc: Daniel Thompson <[email protected]>
Signed-off-by: Guru Das Srinagesh <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The IS_ENABLED() use was missing the CONFIG_ prefix which would have
lead to skipping this code.
Fixes: 3ad1f3a332 ("pwm: Implement some checks for lowlevel drivers")
Signed-off-by: Kees Cook <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
To not trigger the warnings provided by CONFIG_PWM_DEBUG
- use up-rounding in .get_state()
- don't divide by the result of a division
- don't use the rounded counter value for the period length to calculate
the counter value for the duty cycle
Signed-off-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The way state->enabled is computed is rather convoluted and hard to
read - both branches of the if() actually do the exact same thing. So
remove the if(), and further simplify "<boolean condition> ? true :
false" to "<boolean condition>".
Signed-off-by: Rasmus Villemoes <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Even in failed case of pm_runtime_get_sync(), the usage_count is
incremented. In order to keep the usage_count with correct value call
appropriate pm_runtime_put().
Signed-off-by: Navid Emamdoost <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Added support for dynamic clock freq configuration in PWM kernel driver.
Earlier the PWM driver used to cache boot time clock rate by PWM clock
parent during probe. Hence dynamically changing PWM frequency was not
possible for all the possible ranges. With this change, dynamic
calculation is enabled and it is able to set the requested period from
sysfs knob provided the value is supported by clock source.
Changes mainly have 2 parts:
- Tegra186 and later chips [1]
- Tegra210 and prior chips [2]
For [1] - Changes implemented to set pwm period dynamically and also
checks added to allow only if requested period(ns) is below or
equals to higher range.
For [2] - Only checks if the requested period(ns) is below or equals to
higher range defined by max clock limit. The limitation in
Tegra210 or prior chips are due to the reason of having only
one PWM controller supporting multiple channels. But later
chips have multiple PWM controller instances each having
single channel support.
Signed-off-by: Sandipan Patra <[email protected]>
Reviewed-by: Jon Hunter <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The PWM hardware in the JZ4725B works the same as in the JZ4740, but has
only six channels available.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The PWM in Ingenic SoCs starts in inactive state until the internal
timer reaches the duty value, then becomes active until the timer
reaches the period value. In theory, we should then use (period - duty)
as the real duty value, as a high duty value would otherwise result in
the PWM pin being inactive most of the time.
This is the reason why the duty value was inverted in the driver until
now, but it still had the problem that it would not start with the
active part.
To address this remaining issue, the common trick is to invert the
duty, and invert the polarity when the PWM is enabled.
Since the duty was already inverted, and we invert it again, we now
program the hardware for the requested duty, and simply invert the
polarity when the PWM is enabled.
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Calculating the hardware value for the duty from the hardware value of
the period resulted in a precision loss versus calculating it from the
clock rate directly.
(Also remove a cast that doesn't really need to be here)
Fixes: f6b8a57000 ("pwm: Add Ingenic JZ4740 support")
Cc: <[email protected]>
Suggested-by: Uwe Kleine-König <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Depending on MACH_INGENIC prevent us from creating a generic kernel that
works on more than one MIPS board. Instead, we just depend on MIPS being
set.
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Paul Cercueil <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Before commit cfc4c189bc ("pwm: Read initial hardware state at request
time"), a driver's get_state callback would get called once per PWM from
pwmchip_add().
pwm-lpss' runtime-pm code was relying on this, getting a runtime-pm ref for
PWMs which are enabled at probe time from within its get_state callback,
before enabling runtime-pm.
The change to calling get_state at request time causes a number of
problems:
1. PWMs enabled at probe time may get runtime suspended before they are
requested, causing e.g. a LCD backlight controlled by the PWM to turn off.
2. When the request happens when the PWM has been runtime suspended, the
ctrl register will read all 1 / 0xffffffff, causing get_state to store
bogus values in the pwm_state.
3. get_state was using an async pm_runtime_get() call, because it assumed
that runtime-pm has not been enabled yet. If shortly after the request an
apply call is made, then the pwm_lpss_is_updating() check may trigger
because the resume triggered by the pm_runtime_get() call is not complete
yet, so the ctrl register still reads all 1 / 0xffffffff.
This commit fixes these issues by moving the initial pm_runtime_get() call
for PWMs which are enabled at probe time to the pwm_lpss_probe() function;
and by making get_state take a runtime-pm ref before reading the ctrl reg.
BugLink: https://bugzilla.redhat.com/show_bug.cgi?id=1828927
Fixes: cfc4c189bc ("pwm: Read initial hardware state at request time")
Cc: [email protected]
Signed-off-by: Hans de Goede <[email protected]>
Reviewed-by: Andy Shevchenko <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Allwinner A64 is capable of a direct clock output on PWM (see A64 User
Manual chapter 3.10). Add support for this in the sun4i PWM driver.
Signed-off-by: Peter Vasil <[email protected]>
Acked-by: Maxime Ripard <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
This patch adds support for the Azoteq IQS620A, capable of generating
a 1-kHz PWM output with duty cycle between ~0.4% and 100% (inclusive).
Signed-off-by: Jeff LaBundy <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Message logged by 'dev_xxx()' or 'pr_xxx()' should end with a '\n'.
Fixes: 3ad1f3a332 ("pwm: Implement some checks for lowlevel drivers")
Signed-off-by: Christophe JAILLET <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
This driver allows pwms to be requested as gpios via gpiolib. Obviously,
it should not be allowed to request a GPIO when its corresponding PWM is
already requested (and vice versa). So it requires some exclusion code.
Given that the PWMm and GPIO cores are not synchronized with respect to
each other, this exclusion code will also require proper
synchronization.
Such a mechanism was in place, but was inadvertently removed by Uwe's
clean-up in commit e926b12c61 ("pwm: Clear chip_data in pwm_put()").
Upon revisiting the synchronization mechanism, we found that
theoretically, it could allow two threads to successfully request
conflicting PWMs/GPIOs.
Replace with a bitmap which tracks PWMs in-use, plus a mutex. As long as
PWM and GPIO's respective request/free functions modify the in-use
bitmap while holding the mutex, proper synchronization will be
guaranteed.
Reported-by: YueHaibing <[email protected]>
Fixes: e926b12c61 ("pwm: Clear chip_data in pwm_put()")
Cc: Mika Westerberg <[email protected]>
Cc: Uwe Kleine-König <[email protected]>
Cc: YueHaibing <[email protected]>
Link: https://lkml.org/lkml/2019/5/31/963
Signed-off-by: Sven Van Asbroeck <[email protected]>
Reviewed-by: Mika Westerberg <[email protected]>
[cg: Tested on an i.MX6Q board with two NXP PCA9685 chips]
Tested-by: Clemens Gruber <[email protected]>
Reviewed-by: Sven Van Asbroeck <[email protected]> # cg's rebase
Link: https://lore.kernel.org/lkml/20200330160238.GD2817345@ulmo/
Signed-off-by: Thierry Reding <[email protected]>
Fix the following gcc warning:
drivers/pwm/core.c:467:6: warning: symbol 'pwm_apply_state_debug' was
not declared. Should it be static?
Reported-by: Hulk Robot <[email protected]>
Signed-off-by: Jason Yan <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The variable fin_freq is being initialized with a value that is never
read and it is being updated later with a new value. The initialization
is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The TCU channels 0 and 1 were previously reserved for system tasks, and
thus unavailable for PWM.
Signed-off-by: Paul Cercueil <[email protected]>
Tested-by: Mathieu Malaterre <[email protected]>
Tested-by: Artur Rojek <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The TCU registers are shared between a handful of drivers, accessing
them through the same regmap.
While this driver is devicetree-compatible, it is never (as of now)
probed from devicetree, so this change does not introduce a ABI problem
with current devicetree files.
Signed-off-by: Paul Cercueil <[email protected]>
Tested-by: Mathieu Malaterre <[email protected]>
Tested-by: Artur Rojek <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The previous algorithm hardcoded details about how the TCU clocks work.
The new algorithm will use clk_round_rate to find the perfect clock rate
for the PWM channel.
This code relies on the fact that clk_round_rate() will always round
down, which is not a valid assumption given by the clk API, but only
happens to be true with the clk drivers used for Ingenic SoCs.
Right now, there is no alternative as the clk API does not have a
round-down function (and won't have one for a while), but if it ever
comes to light, a round-down function should be used instead.
Signed-off-by: Paul Cercueil <[email protected]>
Tested-by: Mathieu Malaterre <[email protected]>
Tested-by: Artur Rojek <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The ingenic-timer "TCU" driver provides us with clocks, that can be
(un)gated, reparented or reclocked from devicetree, instead of having
these settings hardcoded in this driver.
The new code now uses a clk pointer per PWM (instead of a clk per
pwm-chip before). So the pointer is stored in per-pwm data now.
The calls to arch-specific timer code is replaced with standard
clock API calls to start and stop each channel's clock.
While this driver is devicetree-compatible, it is never (as of now)
probed from devicetree, so this change does not introduce a ABI problem
with current devicetree files.
Signed-off-by: Paul Cercueil <[email protected]>
Tested-by: Mathieu Malaterre <[email protected]>
Tested-by: Artur Rojek <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
'needs_delay' does now always evaluate to true, so remove all
occurrences.
Signed-off-by: Pascal Roeleven <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Implement .apply callback and drop the legacy callbacks(enable, disable,
config, set_polarity). In .apply() check for the current hardware status
before changing the PWM configuration.
Signed-off-by: Lokesh Vutla <[email protected]>
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Only the Timer control register(TCLR) cannot be updated when the timer
is running. Registers like Counter register (TCRR), loader register
(TLDR) and match register (TMAR) can be updated while the counter is
running. Since TCLR is not updated in pwm_omap_dmtimer_config(), do not
stop the timer for period/duty_cycle update.
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
To configure DM timer in PWM mode the following needs to be set in
OMAP_TIMER_CTRL_REG using set_pwm callback:
- Set toggle mode on PORTIMERPWM output pin
- Set trigger on overflow and match on PORTIMERPWM output pin.
- Set auto reload
This is a one time configuration and needs to be set before the start of
the DM timer. But the current driver tries to set the same configuration
for every period/duty cycle update, which is not needed. So move the PWM
setup before enabling timer and do not update it in
pwm_omap_dmtimer_config().
Tested-by: Tony Lindgren <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Update the description with a brief about how PWM is generated using
OMAP DM timer and add limitations for the PWM generations. Also add a
link to the reference manual.
Suggested-by: Uwe Kleine-König <[email protected]>
Acked-by: Tony Lindgren <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
pwm_omap_dmtimer.h is used only:
- to typedef struct omap_dm_timer to pwm_omap_dmtimer
- for macro PWM_OMAP_DMTIMER_TRIGGER_OVERFLOW_AND_COMPARE
Rest of the file is pretty mush unsed. So reuse omap_dm_timer
and OMAP_TIMER_TRIGGER_OVERFLOW_AND_COMPARE in pwm-omap-dmtimer.c
and delete the header file.
Acked-by: Tony Lindgren <[email protected]>
Signed-off-by: Lokesh Vutla <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
During device probe, the message
TPU PWM -1 registered
is printed.
While the "-1" looks suspicious, it is perfectly normal for a device
instantiated from DT.
Remove the message, as there are no non-DT users left, and other drivers
don't print such messages either.
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Runtime PM should be enabled before calling pwmchip_add(), as PWM users
can appear immediately after the PWM chip has been added.
Likewise, Runtime PM should always be disabled after the removal of the
PWM chip, even if the latter failed.
Fixes: 99b82abb0a ("pwm: Add Renesas TPU PWM driver")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Runtime PM should be enabled before calling pwmchip_add(), as PWM users
can appear immediately after the PWM chip has been added.
Likewise, Runtime PM should be disabled after the removal of the PWM
chip.
Fixes: ed6c1476bf ("pwm: Add support for R-Car PWM Timer")
Signed-off-by: Geert Uytterhoeven <[email protected]>
Reviewed-by: Uwe Kleine-König <[email protected]>
Reviewed-by: Laurent Pinchart <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
GPIO core recently added macro to uniformly specify direction of a GPIO
line, so use it.
Signed-off-by: Rishi Gupta <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
The __maybe_unused attribute is preferred over CONFIG_PM to prevent
potential build time issues. This commit replaces CONFIG_PM with this
attribute.
Signed-off-by: Rishi Gupta <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Tegra194 has multiple PWM controllers with each having only one output.
Also the maxmimum frequency is higher than earlier SoCs.
Add support for Tegra194 and specify the number of PWM outputs and
maximum supported frequency using device tree match data.
Signed-off-by: Sandipan Patra <[email protected]>
Acked-by: Uwe Kleine-König <[email protected]>
Acked-by: Laxman Dewangan <[email protected]>
Acked-by: Rob Herring <[email protected]>
Acked-by: Jon Hunter <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Some of the PWM drivers can be compile tested to increase build
coverage.
The Meson PWM driver requires COMMON_CLK dependency.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Florian Fainelli <[email protected]> # For Broadcoam
Reviewed-by: Martin Blumenstingl <[email protected]> # For Meson
Acked-by: Claudiu Beznea <[email protected]> # For Atmel
Acked-by: Uwe Kleine-König <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Linus Torvalds