PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist

In order to do P2P communication the bridge ID of the platform must be in
the P2P device table.

Update the P2P device table with a device ID for the 3rd Gen Intel Xeon
Scalable Processors.

Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Michael J. Ruhl <[email protected]>
Signed-off-by: Bjorn Helgaas <[email protected]>
Reviewed-by: Dan Williams <[email protected]>
This commit is contained in:
Michael J. Ruhl authored and Bjorn Helgaas committed 2022-02-25 11:03:30 -06:00
1 parent e783362eb5
commit feaea1fe8b
1 file changed
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@@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry {
{PCI_VENDOR_ID_INTEL, 0x2032, 0},
{PCI_VENDOR_ID_INTEL, 0x2033, 0},
{PCI_VENDOR_ID_INTEL, 0x2020, 0},
{PCI_VENDOR_ID_INTEL, 0x09a2, 0},
{}
};