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tty: serial: qcom_geni_serial: Add interconnect support

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Get the interconnect paths for Uart based Serial Engine device
and vote according to the baud rate requirement of the driver.

Signed-off-by: Akash Asthana <[email protected]>
Reviewed-by: Matthias Kaehlcke <[email protected]>
Acked-by: Greg Kroah-Hartman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Bjorn Andersson <[email protected]>
This commit is contained in:
Akash Asthana authored and Bjorn Andersson committed 2020-06-24 21:50:17 -07:00
1 parent bf225ed357
commit 7cf563b2c8
1 file changed
+28 -3
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drivers/tty/serial/qcom_geni_serial.c
+28 -3
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@@ -945,6 +945,7 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
struct qcom_geni_serial_port *port = to_dev_port(uport, uport);
unsigned long clk_rate;
u32 ver, sampling_rate;
unsigned int avg_bw_core;
qcom_geni_serial_stop_rx(uport);
/* baud rate */
@@ -966,6 +967,16 @@ static void qcom_geni_serial_set_termios(struct uart_port *uport,
ser_clk_cfg = SER_CLK_EN;
ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
/*
* Bump up BW vote on CPU and CORE path as driver supports FIFO mode
* only.
*/
avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
: GENI_DEFAULT_BW;
port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
geni_icc_set_bw(&port->se);
/* parity */
tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
@@ -1235,11 +1246,14 @@ static void qcom_geni_serial_pm(struct uart_port *uport,
if (old_state == UART_PM_STATE_UNDEFINED)
old_state = UART_PM_STATE_OFF;
if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF)
if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
geni_icc_enable(&port->se);
geni_se_resources_on(&port->se);
else if (new_state == UART_PM_STATE_OFF &&
old_state == UART_PM_STATE_ON)
} else if (new_state == UART_PM_STATE_OFF &&
old_state == UART_PM_STATE_ON) {
geni_se_resources_off(&port->se);
geni_icc_disable(&port->se);
}
}
static const struct uart_ops qcom_geni_console_pops = {
@@ -1337,6 +1351,17 @@ static int qcom_geni_serial_probe(struct platform_device *pdev)
return -ENOMEM;
}
ret = geni_icc_get(&port->se, NULL);
if (ret)
return ret;
port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
/* Set BW for register access */
ret = geni_icc_set_bw(&port->se);
if (ret)
return ret;
port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
"qcom_geni_serial_%s%d",
uart_console(uport) ? "console" : "uart", uport->line);